sgygax Posted January 15, 2018 Report Share Posted January 15, 2018 Hi I'm working with Papilio DUO, Papilio DesignLab 1.0.8 and ZPUino SOft Processor Vanilla v2.0. I'm just testing how much RAM I can use in my sketch. For this reason I increase the size of an array (unsigned char). The sketch below with an array size of 501*1024 bytes is not running. The same sketch with an array size of 500*1024 is working fine. static unsigned char bufferRAM[501*1024]; void setup(){ pinMode(13, OUTPUT); Serial.begin(115200); } void loop(){ digitalWrite(13, HIGH); delay(100); digitalWrite(13, LOW); delay(100); Serial.print(bufferRAM[0]); Serial.println("Hello..."); } Compiler output: Binary sketch size: 515.216 bytes (of a 2.048.000 byte maximum) - 1.728 bytes ROM, 513.640 bytes memory, 25% used Der Sketch verwendet 1.576 Bytes (0%) des Programmspeicherplatzes. Das Maximum sind 2.048.000 Bytes. Globale Variablen verwenden 152 Bytes des dynamischen Speichers. What can be the reason? The Papilio DUO Hardware Guide website says: The ZPUino Soft Processor integrates the SRAM which gives your ZPUino sketches 512KB or 2MByte of code space! Thank you for your help! Quote Link to comment Share on other sites More sharing options...
sgygax Posted January 17, 2018 Author Report Share Posted January 17, 2018 Does it need any more information or explanation? I have 2MB SRAM on the DUO, but I can only use 25% of it (~500KB). Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 17, 2018 Report Share Posted January 17, 2018 Hello sgygax, I'm not in front of a computer to look at this right now, hopefully I can take a look tonight and get back to you. Jack. Quote Link to comment Share on other sites More sharing options...
alvieboy Posted January 18, 2018 Report Share Posted January 18, 2018 My assumption is that the design you use only maps the first 512KB, despite having a larger SRAM. This is probably due to HDL code not properly driving the two extra address lines. Jack: can you check the synthesis/map output to see if the two uppermost address lines are actually driven by the HDL code, or just tied to '0' ? Alvie Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 18, 2018 Report Share Posted January 18, 2018 Sgygax, When you say you are using "ZPUino SOft Processor Vanilla v2.0" can you confirm where you are getting it from? Can you try opening the ZPUino DUO Quickstart sketch and load the ZPUino bit file associated with that sketch to your FPGA and then try your sketch again? Making sure that the board you have selected is the Papilio DUO 2MB... I'm 99% certain that I've run memory tests on that bit file to ensure that all the memory is usable... But it's been a while. Jack. Quote Link to comment Share on other sites More sharing options...
sgygax Posted January 18, 2018 Author Report Share Posted January 18, 2018 Hi Jack It's the samen with the bit file from Papilio DesignLab 1.0.8 -> File -> Examples -> Papilio_DUO_QuickStart on my Papilio DUO 2MB. Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 19, 2018 Report Share Posted January 19, 2018 Ok, I just checked the HDL and the synthesis/map reports and it is definitely mapping 21 pins for a total of 2^21 = 2,097,152 address space... I'm going to have to do testing with an actual board next but unfortunately I closed down the GadgetFactory office about a month ago and everything is still in boxes in a storage space, so I have to dig through boxes to find a 2MB DUO first... We should be able to get this figured out by this weekend at the latest. Jack Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 20, 2018 Report Share Posted January 20, 2018 Hello sgygax, Please give this attached project a try, it is working for me. Be sure to load the circuit included in the attached project to your Papilio DUO board before loading the sketch. All I did is resynthesize the "#define circuit ZPUino_Vanilla" circuit. The pre-synthesized version that is included must have been an older version because when I resynthesized it and looked at the synthesis and map reports it shows that all 21 pins are connected and it works. When I tried your same sketch with the default ZPUino_Vanilla circuit it did not work... Jack. mem_test-180120a.zip Quote Link to comment Share on other sites More sharing options...
sgygax Posted January 21, 2018 Author Report Share Posted January 21, 2018 Hi Jack Thank you very much! It's working now as it should... I have 2MB SRAM on the DUO, and I can use 100% of it :-) Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 22, 2018 Report Share Posted January 22, 2018 Excellent! Glad to hear its working now. Jack. Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.