SergeyS.

SDRAM controller for Papilio Pro

6 posts in this topic

Hello,

I'm a newbie in the FPGA, and I'm managing with the Papilio Pro Board. The problem is I can't make the SDRAM work correctly. I was trying to use the Hamster's SDRAM controller, and did as he describes, but I get weird results.

First, sometimes it reads with random mistakes (though it might be a write problem, I don't know)

Second, sometimes during sequential read it reads first 3-4 values the same and only then starts to increment address.

Could you please advise some VHDL code example of how to explore the Hamster's SDRAM controller (or any other)?

Hamsterworks wiki site doesn't work for some reason so I can't read his explanation once more...

Kind regards,

Sergey

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SDRAM isn't something I'd recommend a newbie try to deal with.  It is tricky, and further complicated by the fact that until read and write both work, nothing works.  Starting with simpler projects is recommended.

I can't point you to any examples meant for teaching, but here are some existing projects, which use the SDRAM, that come to mind; they might be informative.  "socz80" at http://sowerbutts.com/socz80/ uses Hamster's SDRAM controller with a Z80 CPU.  The "ZPUino" port for Papilio Pro also uses that controller, see https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/vanilla/sdram_hamster.vhd and https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/variants/vanilla/sdram_wrap.vhd.  These might also be using different versions of the controller.

I believe clock rate matters for this controller,  ZPUino runs at 96MHz, socz80 at 128MHz; at much lower clock rates it won't operate right.

I've found that anything on an FPGA requires a lot of debugging, it's just something you have to do.

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Try my (ZPUino) SDRAM controller.
You can find here: https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuino/memory/sdram

It uses pipelined wishbone, so make sure you don't hold STB high after your request has been accepted. Also take a look at the PLL settings for it https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/boards/papilio-pro/S6LX9/clkgen.vhd

Any issue drop me an email at alvieboy at alvie dot com

Alvie

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Hi, the latest version of Hamster Controller on his website did not work without a slight modification on the Papilio.

Here is a corrected version, which works for me in several designs on the Papilio:

https://github.com/bonfireprocessor/bonfire-soc/blob/master/sdram/SDRAM_Controller.vhd

The Fix is the "delay_line_length " parameter, which must be 5 for the Papilio. Clock frequency should be ~100Mhz. My version also has an "hold_row_open " parameter, which can improve performance in some applications (end reduce in others...). It holds the active row open until a different row or a refresh is needed. 
 

I also strongly recommend simulating the design, Hamster also has an sdram simulator (you can also get a slightly modified version here: https://github.com/bonfireprocessor/bonfire-soc/blob/master/sdram/sdram_model.vhd).
You can also check with a simulation if your access to the controller works in the right way. If you like I can post a few simulation screen shots here to show how it should work. 

You should also install a bit file of a proven design, like socz80, Zpuino or for example: 

 

(this post contains a "monitor.bit" which you can upload into the Papilio. The boot monitor contains a DRAM test which can be started with the "T" command. 
It is just that you can verify that your Papilio Pro board has no hardware defect (unlikely but not impossible...)

Thomas
 

 

 

 

 

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Hello to all,

Thank you very much for your advises. I was trying to understand both Hamster's SDRAM controllers (simple and extended (ZPuino one)). The last one seems to be quite difficult for understanding for me so far. 

Alvie, could you please give some hints why this huge controller is so... huge? I mean what are its advantages before the simple one? (sorry if my question seems stupid)

I made some success with the simple SDRAM controller, though I still have some random misreads. 

Kind regards,

Sergey

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Hi Sergey,

without referring to the actual source code it is hard to understand to what version of the controller you refer to (especially the "simple" one). As you noticed Hamsters Website is offline, so there is no documentation anymore. 

What I remember from my mind is, that he developed several version of the controller, they differ in complexity of their state machines and their performance. The most basic one he wrote just executed every DRAM access isolated (with opening the row, opening the column, reading/writing and then closing the row and going back to idle state). This is very slow, because every access to the DRAM requires more than 20 clock cycles. 

The more advanced versions support back-to-back read/writes, which means that several sequential accesses to adjacent addresses of the DRAM can be run much faster. 

Actually the latest version of his controller is not really "huge", it is around 550 lines of code and it is well commented. To understand it, you should read the SDRAM chips datasheet it describes quite well how it works. Once you understand it, hamsters controller looks quite straight forward. You should consider using my version of it (see link above), it worked in several Papilio Pro designs right out of the box. I usually use a clock frequency of 96Mhz, believe me, it works. 

I'm sure the Alvies version in zpuino is equally proven, looking in the source code I think it is based on Hamsters "older" design. It requires two phase shifted clocks (which can easily by accomplished), while the 0.6 version creates a phase 180 degrees phase shifted clock internally with the help of a ODDR2 block. The shifted clock is required to compensate for the pcb trace delays and ensuring that the control and data signals are stable when the clock arrives at the DRAM chip ("setup and hold times").  The zupino variant with the extra clock is more complex, but maybe works over a wider clock frequency range, because the phase shift does not depend on the frequency, it keeps constant.  

 I never tried different versions of Hamsters controller, this latest ensures for example that the Flip-Flops in the IO Blocks of the FPGA are used, this is very important for reliable operation. You can verify this in the "Design Overview /IOB Properties" Node in ISE: In Column "Regs" "IFF", "OFF" or both of them must be reported for Inputs/Outputs/Bidirectionals. 

Are you using the SDRAM Controller directly or do you have e.g. a Wishbone interface in between?

Have you tried my advice and simulated the design?

 

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