Rob Bairos

Path of least resistance for beginner..

4 posts in this topic

Hello.
I recently got around to diving into a Papilio Pro I received about 3 years ago.
I struggled through the Windows 10 issues with the missing port/usb detection and the Windows 7 Web Pack ISE crashes.

Im now able to download the Papilio Pro 'hello world' bit file example, and confirms it dumps a default ascii table to a virtual COM port.

I then downloaded DesignLab, but notice there's no Papilio Pro board (just the Papilo Pro / ZPUino ?)  So I think Im out of luck there.

I also have a LogicStart mega wing, and was hoping there was some simple precompiled bit file I could download and verify its working properly.
Does such a thing exist, or do I have to manually create one with the Xilinx ISE and clips Hamsters fpga ebook?

Thanks very much,
Rob.
 

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Alright, so after writing this, I suspected I have to upload the ZPUino image , which this thread seems to say.
I'l dig around that area.
 



 

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Sorry, for anyone following, finally got it working.
Had to select a sketch that supported both the Papilio Pro *and* the LogicStart.
"MegaWing_Logicstart"  was the one.
That's great.  Now I'll start working on some actual vhdl in the ISE.
Cheers

 

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