Jack Gassett

RetroArch running on FPGA.

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The board on picture uses hybrid FPGA+ARM chip Zynq70xx. I guess Retroarch is running on ARM (using Linux OS) while FPGA provides frame buffer + HDMI output. Strictly speaking it's not an FPGA project.

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Unfortunately they say nearly nothing about the project. I think Sorg may be right for the moment, that they just use the ARM cores.  But it can change in the future. I just took a quick look into the Retroarch/Libretro documentation.

To my understanding Retroarch is the frontend (a kind of "Player" for the game engines), while the Libretro cores are the real implementation of the game. The interface between both are on the level of video output and controller input. 

The simplest way is that the core is doing all the rendering and just updates the frontend with every new image. This works for 2D or older games. When running modern 3D games there is an Open GL subset which the core can use. So the rendering in this case is done on the Frontend. Basically this architecture means that a Libretro core can also be implemented in the FPGA fabric (e.g. with a Soft CPU, etc.) and there is just a thin "interface" layer running on the ARM core for communication with the frontend. 

The Zynq 70XX devices did not contain a GPU, so video output is usually also realized in the FPGA fabric, there are predefined IP cores for this purpose which realize a framebuffer in the DDR3 RAM attached to the Zynq. So a possible setup would be to run the video frame buffer / HDMI output in the FPGA fabric, run a game core also in the fabric and use Linux/Retroarch on the ARM for all the mangement between these things. 

So everything is possible. It has the potential to move FPGA retro game implementations out of their nice. There are a lot of aggressively priced Zynq boards now entering the market. I'm even considering using a Zynq board for stand alone FPGA development, they  just have a better price/ performance ratio than many pure FPGA boards.  One additional advantage of the Zynq is that it has a high performance AXI port to the second level cache of the ARM core. One big problem with Softcore implementations  on e.g. an Artix-7 is that without a Cache access to DDR RAM is very slow. But block RAM is to much limited to build a large enough cache. 













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