Jack Gassett

Back to Basics

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Hello everyone, its been quiet in the forums and at GadgetFactory in general. Just wanted to do a quick update and talk about future direction.

First of all, I had a bit of a change up in the last six months. With two new boys in the last couple of years I had to make the decision to move on from working full time on Papilio boards and get a full time job. I've been quiet because it has taken a little time to adjust to working at the new job and continuing work on Papilio boards. I think I finally have things figured out and have a good schedule to work on both. 

Since time is limited I want to focus on getting back to basics with the Papilio FPGA boards. I think that the DesignLab efforts have not really been useful for many people and it is too much to keep maintaining it going forward. The approach of using the schematic editor has just not worked out as well as I hoped it would and overall it is too hard for anyone to contribute to DesignLab. Lesson learned, I need to get back to accepted industry standard techniques and back to VHDL/Verilog going forward. I'd like to start migrating all of the stuff that is currently in DesignLab into smaller and easier to maintain projects. To those ends this is how I'm thinking to proceed:

What is needed (what DesignLab currently does that we want to keep):

  1. A way to manage libraries - people need an easier way to add VHDL/Verilog libraries to their projects then what Xilinx ISE provides. 
  2. A repository for ZPUino Soft Processor projects - DesignLab has several ZPUino SOC projects embedded within it. We need to provide these projects outside of DesignLab.
  3. Arduino Integration - We need to make all the sketches from DesignLab available in the latest version of Arduino IDE or a cloud IDE.
  4. (Nice to have) Continuous Integration for the automatic generation of bit files for the ZPUino projects.
  5. (Nice to have) Xilinx ISE build environment in the cloud.
  6. (Nice to have) Cloud based IDE instead of Arduino IDE.

Ideas to get there:

  1. I like the way node.js manages libraries. I'm thinking to use npm for the libraries and then write node.js code to add libraries to the .xise and .prj files when they are added with npm.
  2. Github is the first place that comes to mind but the problem is that it is too hard to organize projects there. I have so many projects there that it is hard for anyone to find anything and there is no good way to organize projects. GitLab allows directories and subdirectories and they have Continuous Integration functionality built in. Perfect for number 4 above.
  3. The Arduino IDE has come a long way since we forked from it for DesignLab. THey have made it much easier to add custom boards and programmers. There really should be no need for a fork anymore, we just need to make a custom programmer, board type, and libraries.
  4. As mention in 2, GitLab has continuous integration built in. I've already tested it out and have it up and running for a couple ZPUino projects.
  5. I have my own personal Xilinx ISE and ZPUino build environment setup as an AMI at Amazon AWS. When I do any development work I just spin up the AMI as a spot instance at Amazon. When I commit code to GitLab it connects to the runner in the running instance at Amazon and kicks off the build process there. It then published the bin and bit files as artifacts that I can then download and run on my board. I can even see all the build logs... If we could publish an AMI or Docker image that has the entire build environment ready to go and people just download and add a Xilinx license file then this might greatly help alleviate the pain of downloading and setting up the tools. 
  6. What is described in step 5 above is a little tedious when it comes to actually development. It would be nice to use a cloud development IDE like cloud9 for development and have the building happen on a docker instance or something...

Jack.

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This has more or less been my opinion for a while, DesignLab is a neat idea but IMHO it is a huge amount of work to create and maintain while in the end being a dead end that will serve as a crutch enabling people to avoid ever learning HDL and that will become a huge limiting factor down the road. I'm not going to try to tell you what to do but I think it would be great to focus on collecting a library of code a bit like OpenCores, processors, support chips, sound chips, and other interesting widgets that are tested working, and then attempt to clean them up so that they're somewhat consistent and well commented. One of my favorite FPGA projects is the Multicomp by Grant Searle because it is modular and provides a great tutorial on "wiring" up VHDL components into simple but functional computers.

Then there is the larger issue that despite the efforts of many including myself, there seem to be very, very few hobbyist FPGA developers, especially the really talented ones who have developed entire projects. I've tried and largely failed to recruit nearly every technically minded person I know and just haven't succeeded in getting much interest and this frustrates me. Part of this is that FPGA development *is* difficult and there is a very steep learning curve but I think an even bigger obstacle is the perception that it's hard when in actuality putting together a project out of existing modules is not much harder than writing an Arduino program. There is a lot of fragmentation, a number of different FPGA platforms out there, each with their own community and largely the same collection of code, much of which has been circulating for years. Too many people who do create interesting new projects seem reluctant to share their code which is something I find baffling, why bother to create something and show it off if you're not willing to share it?

Anyway I think we need more people involved, more basic tutorials, more Multicomp-like projects, think something like a kit where the main components are already coded and a tutorial is provided to write the code that glues it all together and results in something cool to play with. Maybe drum up some interest in local hackerspaces? A ~2 hour entry level presentation/class? A YouTube channel that presents FPGA exercises? Reverse engineering an existing FPGA project and explaining in detail what each section does? A tutorial to port projects from other FPGA platforms to the Papilio? I've learned a lot by porting various projects from Xilinx to Altera and vice versa. Something to get more people over the initial hump and writing some code, the more people we have contributing, the more interesting stuff there will be for everybody to draw from and contribute to. It's been far too quiet around here recently, I would love to see more people engaging.

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A lot of good advice and ideas. :)

I like Multicomp too, maybe it is a perfect candidate to put up on the new GitLab space and get it doing CI for all the Papilio boards. 

I've been thinking a lot about the libraries idea, it just needs some common way to connect all the pieces together. Maybe wishbone could do the trick, if we make a wishbone connector without a processor that can just send sequential commands to the wishbone bus to set components up and basic tasks... I envision something like how Alvie has ZPUino setup with wishbone slots so you just connect each wishbone component to a slot and then something simple to control it all. Something like the wishbone testbench that Alvie setup too...

But I think the key thing is that I want to work on stuff that people can use...

Jack.

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Hi Jack,

first of all I'm glad to hear that you continue your work.

It sounds a bit ironic that you move away from desgin lab, while Xilinx Vivado goes in the opposite direction. The Vivado IP integrator is like "Designlab on steroids". It is just microblaze and AXI4 instead of zpuino and wishbone.

I never tried designlab but recently bought an Arty board to port my Bonfire project (RISC-V on FPGA, see my forum post...) from Papilio Pro to Arty. At first I was disappointed from Vivado because it has less VHDL support then ISE. But I learned quickly that IP integrator steps in for this. You can integate any HDL as "RTL module" in IP integrator, and use the block design to wire the toplevel together. With this I had my processor running together with DDR3 RAM and Ethernet in two weeks. Of course this is far away from the open source idea, but with all the core synthesis work done by propietary Xilinx tool FPGA development is never true open source.

But this is all more a side note. What personally I really like on the GadgetFactory is your hardware. I ordered a second Papilio Pro a few weeks ago, because it is the most "hacking friendly" FPGA board on the market (at least for Xilinx chips). It can be leveraged completely with comparable easy to understand open source HDL, e.g Hamsters SDRAM controller. Compare this with the Arty, the DDR3 RAM can only be managed practically with a Xilinx MIG which consumes 25% of the slices and increases synthesis times a lot.  And for many usages patterns it is even slower then  SDR SDRAM.

An upgraded Papilio with a series 7 FPGA would be a dream, of course I have read about the difficulties of BGA...

It would also open the path to Vivado, and Vivado could be helpful with your HDL library idea. Especially because Vivado IP cores are based on IP XACT. With FuseSOC  https://github.com/olofk/fusesoc there is also an open source package manager supporting IP XACT. I have not used it, but I think it goes in the direction you are aiming for.

I have doubts that additional tools like you mentioned in your roadmap really help, they make things more complicated then easier. 

Some, very subjective words on Arduino: While Arduino is a fantastic idea, the Arduino IDE itself is really crap. It is on the level of Turbo Pascal for CP/M in 1983. While this was a great idea in 1983, it is not in 2017. 

Regarding your idea with an AMI image: why not making the same with a virtual box VM? Cloud is fine, but quickly cost a lot of  money:-)

Thomas

 

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On 19.9.2017 at 8:09 PM, james1095 said:

Then there is the larger issue that despite the efforts of many including myself, there seem to be very, very few hobbyist FPGA developers, especially the really talented ones who have developed entire projects. I've tried and largely failed to recruit nearly every technically minded person I know and just haven't succeeded in getting much interest and this frustrates me. Part of this is that FPGA development *is* difficult and there is a very steep learning curve but I think an even bigger obstacle is the perception that it's hard when in actuality putting together a project out of existing modules is not much harder than writing an Arduino program. 

 

Well, I think that people find FPGA development hard and difficult has is root cause that they don't understand the difference between hardware and software. Because HDLs borrow many syntactical  constructs from programming languages and the code looks like a "program" (this is especially true for VHDL) people think in the wrong direction and get very frustrated. In the moment you realize that it describes hardware and think about expressions as a bunch of gates and signals set in a synchronous process as flip-flops it becomes easy. I personally can write and debug VHDL code as fast and productive as C code. Ok thinks get much harder in the moment you go off-chip. 

It is possible to write software without ever really understanding how it is really executed in a computer. I know developers who have difficulties to understand what is really the difference between an integer and a float or why it sometimes go wrong when you assign a short to a long :-)

It is possible to write software with this limited level of understanding (in fact most JavaScript, php or python code is written by such people ), but it is not possible with Hardware. Even worse, without understanding the concepts it is even impossible to recognize the value of FPGA. 

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1 hour ago, Thomas Hornschuh said:

Hi Jack,

first of all I'm glad to hear that you continue your work.

It sounds a bit ironic that you move away from desgin lab, while Xilinx Vivado goes in the opposite direction. The Vivado IP integrator is like "Designlab on steroids". It is just microblaze and AXI4 instead of zpuino and wishbone.

Haha, yes I actually wanted to use Vivado when I started making DesignLab... Wish it supported Spartan 6 chips.

Quote

I never tried designlab but recently bought an Arty board to port my Bonfire project (RISC-V on FPGA, see my forum post...) from Papilio Pro to Arty. At first I was disappointed from Vivado because it has less VHDL support then ISE. But I learned quickly that IP integrator steps in for this. You can integate any HDL as "RTL module" in IP integrator, and use the block design to wire the toplevel together. With this I had my processor running together with DDR3 RAM and Ethernet in two weeks. Of course this is far away from the open source idea, but with all the core synthesis work done by propietary Xilinx tool FPGA development is never true open source.

But this is all more a side note. What personally I really like on the GadgetFactory is your hardware. I ordered a second Papilio Pro a few weeks ago, because it is the most "hacking friendly" FPGA board on the market (at least for Xilinx chips). It can be leveraged completely with comparable easy to understand open source HDL, e.g Hamsters SDRAM controller. Compare this with the Arty, the DDR3 RAM can only be managed practically with a Xilinx MIG which consumes 25% of the slices and increases synthesis times a lot.  And for many usages patterns it is even slower then  SDR SDRAM.

An upgraded Papilio with a series 7 FPGA would be a dream, of course I have read about the difficulties of BGA...

I would jump on a series 7 chip and deal with the BGA issues in a heartbeat. The problem is that the prices are still very high and its not easy for my manufacturers to get them... Right now the cheapest Artix-7 chip on Digikey is $35. I jumped on the Spartan-6 chips for the Papilio FPGA when I saw them on Digikey for less then $20 and I would do the same for the Artix-7. I've been itching to make an Artix-7 board. :)

Quote

It would also open the path to Vivado, and Vivado could be helpful with your HDL library idea. Especially because Vivado IP cores are based on IP XACT. With FuseSOC  https://github.com/olofk/fusesoc there is also an open source package manager supporting IP XACT. I have not used it, but I think it goes in the direction you are aiming for.

Ok, this is on my todo list to check out. :) I would also like to see about getting your Bonfire project setup with continuous integration too. Need to look closer at both of them again. 

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I have doubts that additional tools like you mentioned in your roadmap really help, they make things more complicated then easier. 

Yes, want to avoid complication for sure. DesignLab was guilty of that, don't want to do it again.

Quote

Some, very subjective words on Arduino: While Arduino is a fantastic idea, the Arduino IDE itself is really crap. It is on the level of Turbo Pascal for CP/M in 1983. While this was a great idea in 1983, it is not in 2017. 

Agree completely, the IDE is terrible, but the libraries and ecosystem are great. We could eliminate the Arduino IDE entirely and go with a web based IDE like Cloud9 or a non-web based IDE like Atom and have a much nicer environment. The challenge is to find a way to program the board. Alvie and I are working on a new Papilio board called Unity that is entirely serial based and has a bootloader like the Arduino. This would be easier to integrate into a cloud IDE...

Quote

Regarding your idea with an AMI image: why not making the same with a virtual box VM? Cloud is fine, but quickly cost a lot of  money:-)

Thomas

 

Well, given enough time I would redo what I have already done using Packer. Then you can use vagrant to quickly start it up in virtual box, AWS, Parallels, or VMWare. Or go with a docker image... I mention AMI because I already have it up and running. The thing I forgot to mention in my initial post is that it is very cheap to run the AMI as a spot instance. I'm paying about 1 to 10 cents an hour for a AWS instance that synthesizes the ZPUino bit file in around 2 to 4 minutes. That's faster then my development box does... If I left it running all month it would cost ~$7 dollars. The trick is to terminate the instance when you are done so you don't leave disk space laying around unused. That is where they get you with the fees, if you shut down instead of terminate you continue to be charged a hefty fee for the hard drive space that is still allocated. Do a terminate and it frees up the hard drive space and avoids continuous charges.

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I may be showing my age but I absolutely loathe nearly any kind of web based software. There are certain things it is convenient for, checking email when I'm away from my own PC with a proper desktop client, occasionally a simple tool, but for any kind of productivity software I find it frustrating. It's always slower, invariably I seem to have to do a lot of scrolling, it never seems to work equally well in all browsers, then for reasons I've never been able to fathom many browsers interpret the backspace key as navigate back to the previous page causing you to lose all the data. I'm forced to use a lot of web based crap at work and I never have taken to liking it. Especially these days when vastly powerful PCs with massive hard drives and gobs of RAM cost peanuts I'm baffled by the trend to return the the mainframe-dumb terminal paradigm. I guess what's old enough is new.

 

That said, I suppose it doesn't really matter to me, I'm pretty content using ISE for my Papilio boards. I'd much rather spend any time I have writing code rather than learning a new tool. VHDL and Verilog are industry standards, code written in a standard language can be synthesized on any suitably large FPGA with minimal changes. With so few developers in the community it's essential to minimize fragmentation.

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33 minutes ago, Jack Gassett said:

Agree completely, the IDE is terrible, but the libraries and ecosystem are great. We could eliminate the Arduino IDE entirely and go with a web based IDE like Cloud9 or a non-web based IDE like Atom and have a much nicer environment. The challenge is to find a way to program the board. Alvie and I are working on a new Papilio board called Unity that is entirely serial based and has a bootloader like the Arduino. This would be easier to integrate into a cloud IDE...

The libraries are a fantastic aspect of the Arduino and the key thing that makes it a worthwhile if otherwise rather flawed platform. It took me a long time to warm up to Arduino but I love the way I can grab some widget and very often grab a library with example code to make it do something right away. It provides a great way to test the thing out and explore its capabilities right off the bat. I'd love to see a similar collection of HDL modules form, blocks of code that do the grunt work like initializing the device and communicating via whatever interface it uses and bring the controls out to sensible interfaces that can be tied into other modules in the top level file. Ideally these modules should be well commented, especially at the top level explaining what all the inputs and outputs do and what sort of signals they expect.

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16 hours ago, Jack Gassett said:

 

I would jump on a series 7 chip and deal with the BGA issues in a heartbeat. The problem is that the prices are still very high and its not easy for my manufacturers to get them... Right now the cheapest Artix-7 chip on Digikey is $35. I jumped on the Spartan-6 chips for the Papilio FPGA when I saw them on Digikey for less then $20 and I would do the same for the Artix-7. I've been itching to make an Artix-7 board. :)

How about Spartan-7? There are now available to.  With the Arty-S7 Digilent has the first board with it. It it basically Artix-7 without high speed transceivers. I'm also seeing a lot of relatively cheap Zynq boards reaching the market. Also from smaller companies (e.g. the "Zynqberry" from Trenz Electronic in Germany). I have the feeling that Xilinx markets Zynq very aggressive and when I compare the price of Zynq boards with Artix  boards I assume that the smaller Zynq devices (especially the Single Core Zynq-7007) are cheaper than Artix.

On one side Zynq adds a lot of complexity to an FPGA board, on the other side it can help to create a more user friendly experience. I have not worked with Zynq on my own (but I'm sure I will not resist the temptation to buy one of those cheap Zynq boards very long...), but my understanding is that the Zynq processing system can configure the PL (the FPGA part of the Zynq). So uploading a design over e.g. network, could be possible. No more complicated JTAG stuff...

One of the big advances of Vivado over ISE is that Xilinx has changed the licensing policy. The free Webpack is not limited by features anymore, it is limited by size and type of the device. The devices they don't support are mostly beyond the reach of a hobby user :-) So I have ILO (former Chipscope), full Microblaze+ SDK,  full featured simulator and so on.  The disadvantage is that classic HDL design is not well supported anymore (no vhi and test bench generation, harder to use syntax check, less informative synthesis messages, no bmm file support for non-Microblaze designs) and at least on my systems Vivado crashes more often. I now use both. ISE for basic HDL design and "unit testing", Vivado for integration and verification on hardware)

For CI flows it may help that vivado can easier be used as command line tool with tcl scripts in "non-project" mode. I'm currently in the process of finding out a way to integrate vivado in a classic "make" project where I can say "make all" to compile the boot monitor, synthesize the bit stream, compile eLua and putting it all together  into an MCS file which I can load onto Arty. 
Because I have also a full network stack in eLua I'm considering to allow Update over the network. It should be possible to write that the Soft SOC system write a new bitstream to address 0 of the flash and then restart the FPGA. But still more ideas than I can manage in my limited spare time :)

BTW: Maybe you like to take a look in my just starting youtube channel: https://www.youtube.com/channel/UCkcJwz3oPKh60YKUc4zs6CQ

Please excuse the async audio, all screen grabbing tools I tried under Linux are horrible (maybe because it is a VM) and my German accent ;)

Thomas

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I think for a beginner oriented board like the Papilio series a newer, larger, more powerful FPGA may be more of a curse than a benefit. Amongst my collection of FPGA boards I find that the two most powerful, a PrimeSense with Virtex5 and a DE2-115 with a large Cyclone IV hardly ever get used for anything. None of my designs come anywhere close to needing such a large FPGA and regardless of what I do with it, the larger more complex devices take longer to compile for, in some cases dramatically so. With so many soft core processors out there I've never even bothered to try the Microblaze or NIOS cores, I've just never had a reason. It would be nice if Xilinx would change the licensing terms for the ISE Webpack to match those of Vivado, all it would take is offering a different license file. Frankly I've never understood why they have any restrictions at all, just give away the fully featured software for personal use and have paid support subscriptions for commercial users like all the microcontroller manufactures. Give away the software for free because it sells hardware which is their core business. Aggressively court hobbyists and students because some of them go on to become engineers and they are likely to keep using the product lines they are familiar with.

Anyway, back on topic. What the Papilio boards do lack is IO and memory. The Pro has SDRAM but that does not lend itself easily to retro hardware which is my primary interest. Block RAM within the FPGA is a scarce and precious resource and 95% of the time it's a lack of sufficient memory that prevents a design from fitting in a smaller FPGA. Having external SRAM and ROM or sufficient IO pins to add it opens the door to many more projects.

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I think for a beginner oriented board like the Papilio series a newer, larger, more powerful FPGA may be more of a curse than a benefit. 

I don't think so, at least when you upgrade in the area what Xilinx call "cost sensitive portfolio", which means Artix and Spartan. Basically a larger FPGA is not more complex, it has just more macro cells.  When you think about Retro computing when going from 8 to 16/32 Bit systems (like Amiga/Mac/Atari ST for all them also exist FPGA implementations) you can leverage the 20-50K "cells" devices. Of course devices like Kintex and Virtex have features which are of no use in this area and in best case a waste of money. Place and Route times increase quadratically with the size of the device, also the memory required to run this process, but this will only happen when your design really needs the area. 

Quote

 With so many soft core processors out there I've never even bothered to try the Microblaze or NIOS cores, I've just never had a reason.

Well I also do not really use them. As somebody mainly interested in processor design I also prefer to run my own soft cores. But the way Vivado integrates Microblaze is for me the "gold standard" on ease-of-use which I also aim for my own designs. You can just place in the Microblaze into IP integrator, drop in your peripherals, memory, etc., edit the address space map and run synthesis. Then jump to the SDK, it reads an automatically created hardware description file and knows what is on your chip and configures everything. If you have an ethernet core on the board, you can just use uIP to establish a TCP/IP connection. There are people out which are not interested in processors, they may do something else with the FPGA. They may have some cool IoT idea and just need  a workhorse to connect their idea to the internet. And Microblaze is just this workhorse. My idea of course is that my Bonfire Processor https://github.com/bonfireprocessor/bonfire is this workhorse ;)

I'm now at least at the point that it is "plug" compatible with Microblaze (of course not Software compatible...). The part doing this is not yet on GitHub...

And yes the half automated Vivado IP design requires more resources than its traditional manually crafted VHDL counterpart on the Papilio Pro without necessarily been more powerful. But productivity is much higher and I think  the learning curve is less steep.  

Quote

Frankly I've never understood why they have any restrictions at all, just give away the fully featured software for personal use and have paid support subscriptions for commercial users like all the microcontroller manufactures.

Well I had a chance to discuss this with a Xilinx employee a while ago. FPGAs are different than microcontrollers. There are volume devices, like e.g. the Spartan, where they make the money with selling chips like most chip manufacturers. 

But there are a lot of customers using the really expensive super high-end FPGAs for things like prototyping and simulation of ASICs, science experiments (e.g. particle detectors). In this type of applications the money is earned with tools, support and professional services.  Vivado licensing works in this way: For the volume chips you can use Webpack, for the high-end chips you have to pay a premium price (for the chip and the tools...)

But I think FPGAs are inherently niche products which makes them expensive. There are uses case where they are without any competition, but these cases are rare. On volume applications they compete with ASICs, on low-volume and very-low volume applications they compete with Software. Retro-Computing is also such a niche. FPGAs compete with software emulators. Much more people use an emulator to run a retro computer, than an FPGA. Today's computers are so powerful that a Javacsript  application in a browser can emulate a Macintosh faster than realtime

 

 

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22 hours ago, james1095 said:

I may be showing my age but I absolutely loathe nearly any kind of web based software. There are certain things it is convenient for, checking email when I'm away from my own PC with a proper desktop client, occasionally a simple tool, but for any kind of productivity software I find it frustrating. It's always slower, invariably I seem to have to do a lot of scrolling, it never seems to work equally well in all browsers, then for reasons I've never been able to fathom many browsers interpret the backspace key as navigate back to the previous page causing you to lose all the data. I'm forced to use a lot of web based crap at work and I never have taken to liking it. Especially these days when vastly powerful PCs with massive hard drives and gobs of RAM cost peanuts I'm baffled by the trend to return the the mainframe-dumb terminal paradigm. I guess what's old enough is new.

 

That said, I suppose it doesn't really matter to me, I'm pretty content using ISE for my Papilio boards. I'd much rather spend any time I have writing code rather than learning a new tool. VHDL and Verilog are industry standards, code written in a standard language can be synthesized on any suitably large FPGA with minimal changes. With so few developers in the community it's essential to minimize fragmentation.

Just give Cloud9 a quick look, I worked on a web site using this tool recently and it was really great... The big change is that the entire development environment is included with the IDE, so you don't have to install a thing on your desktop to be up and running quickly...

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6 hours ago, Thomas Hornschuh said:

 

How about Spartan-7? There are now available to.  With the Arty-S7 Digilent has the first board with it. It it basically Artix-7 without high speed transceivers. I'm also seeing a lot of relatively cheap Zynq boards reaching the market. Also from smaller companies (e.g. the "Zynqberry" from Trenz Electronic in Germany). I have the feeling that Xilinx markets Zynq very aggressive and when I compare the price of Zynq boards with Artix  boards I assume that the smaller Zynq devices (especially the Single Core Zynq-7007) are cheaper than Artix.

Oh! I had forgotten about Spartan-7... But just checked on Digikey ant they are $50.... Needs to be a cheaper supply available.

6 hours ago, Thomas Hornschuh said:

On one side Zynq adds a lot of complexity to an FPGA board, on the other side it can help to create a more user friendly experience. I have not worked with Zynq on my own (but I'm sure I will not resist the temptation to buy one of those cheap Zynq boards very long...), but my understanding is that the Zynq processing system can configure the PL (the FPGA part of the Zynq). So uploading a design over e.g. network, could be possible. No more complicated JTAG stuff...

One of the big advances of Vivado over ISE is that Xilinx has changed the licensing policy. The free Webpack is not limited by features anymore, it is limited by size and type of the device. The devices they don't support are mostly beyond the reach of a hobby user :-) So I have ILO (former Chipscope), full Microblaze+ SDK,  full featured simulator and so on.  The disadvantage is that classic HDL design is not well supported anymore (no vhi and test bench generation, harder to use syntax check, less informative synthesis messages, no bmm file support for non-Microblaze designs) and at least on my systems Vivado crashes more often. I now use both. ISE for basic HDL design and "unit testing", Vivado for integration and verification on hardware)

For CI flows it may help that vivado can easier be used as command line tool with tcl scripts in "non-project" mode. I'm currently in the process of finding out a way to integrate vivado in a classic "make" project where I can say "make all" to compile the boot monitor, synthesize the bit stream, compile eLua and putting it all together  into an MCS file which I can load onto Arty. 
Because I have also a full network stack in eLua I'm considering to allow Update over the network. It should be possible to write that the Soft SOC system write a new bitstream to address 0 of the flash and then restart the FPGA. But still more ideas than I can manage in my limited spare time :)

Yes, I would really love to move to Vivado, that is where everything new is at now...

6 hours ago, Thomas Hornschuh said:

BTW: Maybe you like to take a look in my just starting youtube channel: https://www.youtube.com/channel/UCkcJwz3oPKh60YKUc4zs6CQ

Nice, I'm putting on my list of urls to check for content to post to GF blog...

6 hours ago, Thomas Hornschuh said:

Please excuse the async audio, all screen grabbing tools I tried under Linux are horrible (maybe because it is a VM) and my German accent ;)

Thomas

 

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6 hours ago, james1095 said:

Anyway, back on topic. What the Papilio boards do lack is IO and memory. The Pro has SDRAM but that does not lend itself easily to retro hardware which is my primary interest. Block RAM within the FPGA is a scarce and precious resource and 95% of the time it's a lack of sufficient memory that prevents a design from fitting in a smaller FPGA. Having external SRAM and ROM or sufficient IO pins to add it opens the door to many more projects.

The new Papilio Unity board tries to solve the memory problem by letting you add different memory modules, depending on what you want to do. For retro projects or easy to use RAM then there is a SRAM module. For lots of memory there is SDRAM module. For even more, we can make a DDR module.

IMG_0724.JPG

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On 9/20/2017 at 5:16 PM, Jack Gassett said:

I would jump on a series 7 chip and deal with the BGA issues in a heartbeat. The problem is that the prices are still very high and its not easy for my manufacturers to get them... Right now the cheapest Artix-7 chip on Digikey is $35. I jumped on the Spartan-6 chips for the Papilio FPGA when I saw them on Digikey for less then $20 and I would do the same for the Artix-7. I've been itching to make an Artix-7 board. :)

At work we have switched most of our Spartan-6 products to Artix-7 and for the most part the switch-over was painless, the only area that needed a bit work was places in the code where we directly instantiated low level design elements (like serdes blocks, BSCAN_SPARTAN6 etc.) that had to be re-coded using 7 series elements, and the new way of setting contstrains.  However, one area that Xilinx keep messing up is LVDS outputs, which we use lots of.  On the Spartan-6 part that we used, only 2 of the 4 banks could have LVDS outputs.  On Artix-7 all banks can have LVDS outputs but the bank must have VCCIO set to 2.5V!  This means that Digilent boards like Arty and CMOD A7 and Avnet boards like miniZed etc. can't do LVDS output at all since all banks are powered by 3.3V! This is pretty lame since LVDS is the future for high speed I/O, just look at UHS-II sd-card standard where 2 LVDS pairs are added for high speed applications.

As for my FPGA "hobby" busyness, I have no desire to develop an Artix-7 or Zynq based board and compete with heavily subsidized products from Digilent and Avnet.  And there won't be any more Spartan-6 based boards made by me either (Pipistrello LX45 and Pepino LX25 are sold out and discontinued and once the Pepino LX9 boards are sold there won't be any more boards made). End of the road...

On 9/19/2017 at 11:09 AM, james1095 said:

DesignLab is a neat idea but IMHO it is a huge amount of work to create and maintain while in the end being a dead end that will serve as a crutch enabling people to avoid ever learning HDL and that will become a huge limiting factor down the road.

I totally agree. I have a long history of designing custom chips, starting in the 1980's with schematic-based design entry for ASICs.  When we switched to text-based design entry (i.e. HDL) in the 1990's the productivity gain was incredible.  We could do much more complex designs and still understand what it did, and we could use all the tools developed for software to maintain the code (like CVS for code repository, using the text editor that we liked most for design entry, and simple things like text compare).  Going back to schematic-based design entry is in my mind a huge step back.

Magnus

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19 hours ago, Jack Gassett said:

Just give Cloud9 a quick look, I worked on a web site using this tool recently and it was really great... The big change is that the entire development environment is included with the IDE, so you don't have to install a thing on your desktop to be up and running quickly...

As far as web based stuff goes the UI looks nice, but it still doesn't solve the issue that I am away from reliable (or any) internet access just often enough that I don't want to rely on it for anything that I can run locally. If a proper desktop application is available I will always use it, web based stuff is a backup that is convenient when I'm not on my own PC.

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1 hour ago, mkarlsson said:

I totally agree. I have a long history of designing custom chips, starting in the 1980's with schematic-based design entry for ASICs.  When we switched to text-based design entry (i.e. HDL) in the 1990's the productivity gain was incredible.  We could do much more complex designs and still understand what it did, and we could use all the tools developed for software to maintain the code (like CVS for code repository, using the text editor that we liked most for design entry, and simple things like text compare).  Going back to schematic-based design entry is in my mind a huge step back.

Magnus

I think there is *some* value in the schematic based entry, for a total beginner it provides a way to make the FPGA or CPLD "do something" and helps to drive home the point that you are designing hardware rather than writing a program. It's not a bad idea to do a few simple projects using the schematic, but then move on to HDL as soon as you get beyond stuff like blinking LEDs.

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3 hours ago, mkarlsson said:

 

As for my FPGA "hobby" busyness, I have no desire to develop an Artix-7 or Zynq based board and compete with heavily subsidized products from Digilent and Avnet.  And there won't be any more Spartan-6 based boards made by me either (Pipistrello LX45 and Pepino LX25 are sold out and discontinued and once the Pepino LX9 boards are sold there won't be any more boards made). End of the road...

I can understand that. With boards like the Arty series the market for small hobby board vendors like you and Jack gets a lot tighter. The price for these boards is unbeatable and they are fully integrated into the Xilinx tools with board description files, etc. And they are almost always in stock. But I think it is also a big loss in diversty on the market. Albeit all boards use the same FPGAs the peripherals also matter. If I compare your boards with Jacks and maybe Xess, Numato, etc, they are all different with all their strengths and weaknesses.

Maybe I should by a Pepino before it is completely sold out;)

It is also really unique with 32Bit wide SRAM and all its I/O. It is the perfect Retro computing platform. And for the Oberon Fans (I don't know if there are many...) it will be sad. 

Thomas

 

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Well one of the big advantages of open source hardware is that anyone can build more of them any time they want provided the components are still available.

I see two sides to the hardware situation. On one hand it's always nice to have options, but on the other hand the FPGA development community is so small as it is and every additional platform out there creates further fragmentation. In general I would say that it's a better use of resources to work on the collection of projects that run on the FPGAs rather than creating even more competing hardware platforms. An exception to this, and one that I think Gadget Factory could really excel at is producing peripheral modules to work with the FPGA boards already out there. The Papilio wings are the obvious place to start but it may make sense to expand to some of the various little Chinese dev boards that are out there. It would be great to see more widgets in wing format complete with some example HDL to make them do something out of the box.

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5 hours ago, mkarlsson said:

As for my FPGA "hobby" busyness, I have no desire to develop an Artix-7 or Zynq based board and compete with heavily subsidized products from Digilent and Avnet.  And there won't be any more Spartan-6 based boards made by me either (Pipistrello LX45 and Pepino LX25 are sold out and discontinued and once the Pepino LX9 boards are sold there won't be any more boards made). End of the road...

It is definitely tough to compete with the subsidized boards that are out there... It was a sad day when I came to the realization that I couldn't support my family with Open Source FPGA boards anymore and had to get a job doing something else. I'm sorry to hear you are discontinuing your boards, I've been pretty close myself too. It's been a real struggle to pay for inventory, it's turned around now that I have started a job and all profits from sales are going right back into buying inventory. The Papilio Unity is also meant to simplify the product line and make it more affordable to keep stocked. It is meant to replace the Papilio One 250K, 500K, and the Papilio Pro with a single board. It will hopefully be low cost like the Papilio One 250K when bought without memory, using the bootloader and a non switching power supply should really bring down the costs. Then it can also be expanded into the Papilio Pro with SRAM or SDRAM.

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22 minutes ago, james1095 said:

Well one of the big advantages of open source hardware is that anyone can build more of them any time they want provided the components are still available.

I see two sides to the hardware situation. On one hand it's always nice to have options, but on the other hand the FPGA development community is so small as it is and every additional platform out there creates further fragmentation. In general I would say that it's a better use of resources to work on the collection of projects that run on the FPGAs rather than creating even more competing hardware platforms. An exception to this, and one that I think Gadget Factory could really excel at is producing peripheral modules to work with the FPGA boards already out there. The Papilio wings are the obvious place to start but it may make sense to expand to some of the various little Chinese dev boards that are out there. It would be great to see more widgets in wing format complete with some example HDL to make them do something out of the box.

Wings have always been the least popular item I sell which I always found surprising, maybe PMods were just a better execution with more resources behind it... I was trying to get GadgetBox and the concept of eCogs off the ground to appeal to a larger audience. Then I would merge Wings and eCogs together down the road. It's something that I still hope to do, but it will take a little longer to do now as I dig myself out of the hole I found myself in. :)

I'm taking the approach now of really trying to see how I can put something together that provides value as an entire solution. Before I would just focus on making a wing when it was needed by a certain application I had in mind. It was useful to me in that moment but I didn't conceive of it from the beginning as to how I could make something that would be useful to people. Now I'm trying to go the other direction, how can I put a system in place that is useful for people, like implementing FuseSOC and a cloud building service, and then making Wings or eCogs to fit within that framework...

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1 hour ago, Jack Gassett said:

Wings have always been the least popular item I sell which I always found surprising, maybe PMods were just a better execution with more resources behind it... 

I think the problem with Wings is similar to Arduino shields:  They almost never fit. Either something needed is missing, or there is something unneeded which occupy I/O pins which may be needed for other purposes. I did some work with Arduinos but never bought a shield. I often buy small breakout boards for a single purpose, e.g. sensor boards, realtime clocks, etc. 

Thomas

 

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Jack,

I have been very frustrated because  I can't seem to get by the development environment hurdles, and my attempts to get help from you have not been successful.  I have all but given up asking for help, and figure I will need to just figure out things by myself.  The two things I tried unsuccessfully to get help from you are:

1) How to get your Wishbone version of the Sump Logic analyzer to compile without errors.  I follow your instructions but it doesn't work.  If I could just get this code to run, it would be a fantastic learning vehicle.

2) How to write VHDL code to write to the 2MB SRAM through the Wishbone interface so it can be read by the Zpuino.

Also, when I try to build lots of the example projects, I get compilation errors.

The bottom line is, I think your boards and resources are great, but the videos on your learn page are not enough for me to really become proficient enough to overcome the errors I get when trying examples that are supposed to work.

By the way, will your new development environment support the old boards such as the DUO and 250K?

Regards,

Blake

 

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Jack is just one guy, rather than relying on him personally to solve your problems I suggest posting individual questions for the specific problems you're having. FPGA development has a steep learning curve, it took me more than a year of struggling before I really started to get the hang of things. A lot of the errors the compiler spits out are cryptic and not very helpful, often they don't even point to the root cause but are the result of a chain of events back to an error made up higher.

 

What errors are you seeing with the logic analyzer? What errors are you getting when you try to build the other example projects?

 

I can't be of much help with the Zpuino because I've never used it, but SRAM is straightforward to use.

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For the example which I would really like to get work, I refer to the Feb 20 post that Jack made under the topic "Wishbone version of the Sump Blaze Logic Analyzer".  When I click on edit circuit, ISE hangs, but I can see what it was trying to do, so I open I start ISE by itself and open the project that it hung on, which is DesignLab/OLS_Client/circuit/PSL_Papilio_DUO_LX9.xise.  However, this project seems to have all the library code, not just that related to the Wishbone logic analyzer.  Shouldn't there be a project that just has the Sump Logic analyzer project?  What I really want to do is poke around and make modifications to the VHDL code in this project.

Blake

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