Jack Gassett

Back to Basics

44 posts in this topic

6 hours ago, bnusbick said:

Jack,

I have been very frustrated because  I can't seem to get by the development environment hurdles, and my attempts to get help from you have not been successful.  I have all but given up asking for help, and figure I will need to just figure out things by myself.  The two things I tried unsuccessfully to get help from you are:

I'm sorry you have been frustrated, and I totally understand how it is frustrating, but the things you are asking for are far from trivial... Both items you list below were experimental things that Alvie and I were working on and then never completed. We posted them to the forums hoping that someone would have some time to pick them up and work on them. I spent a couple weeks of full time work getting them to the point they were and it would take several more weeks to get them completed. Unfortunately I don't have that kind of time anymore. So all I can do is point you in the right direction with those projects and hope for the best. 

6 hours ago, bnusbick said:

1) How to get your Wishbone version of the Sump Logic analyzer to compile without errors.  I follow your instructions but it doesn't work.  If I could just get this code to run, it would be a fantastic learning vehicle.

2) How to write VHDL code to write to the 2MB SRAM through the Wishbone interface so it can be read by the Zpuino.

Also, when I try to build lots of the example projects, I get compilation errors.

The bottom line is, I think your boards and resources are great, but the videos on your learn page are not enough for me to really become proficient enough to overcome the errors I get when trying examples that are supposed to work.

Both examples you list above are not examples that are supposed to just work... They were things we were working on and were in a somewhat working state but not well tested and not meant to be an example that just works.

6 hours ago, bnusbick said:

By the way, will your new development environment support the old boards such as the DUO and 250K?

Absolutely, I plan to phase out the 250K so probably won't bring forward examples for that board, but the DUO will get the same treatment as the Papilio Unity for sure.

6 hours ago, bnusbick said:

Regards,

Blake

 

 

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2 hours ago, bnusbick said:

For the example which I would really like to get work, I refer to the Feb 20 post that Jack made under the topic "Wishbone version of the Sump Blaze Logic Analyzer".  When I click on edit circuit, ISE hangs, but I can see what it was trying to do, so I open I start ISE by itself and open the project that it hung on, which is DesignLab/OLS_Client/circuit/PSL_Papilio_DUO_LX9.xise. 

So the key here is that we really need to get to the bottom of why ISE hangs when you click on edit circuit. It won't work to just open up the *.xise file itself because when you click on edit circuit DesignLab is putting all of the necessary library files into the *.xise file. If you just open it directly it will not have any of the files that you need. 

2 hours ago, bnusbick said:

 

However, this project seems to have all the library code, not just that related to the Wishbone logic analyzer.  Shouldn't there be a project that just has the Sump Logic analyzer project?  What I really want to do is poke around and make modifications to the VHDL code in this project.

Blake

That is the other problem/shortcoming with DesignLab. Even if you get the project to open it is not going to be obvious at all where you need to go to see the relevant VHDL files... You will need to know to push into the Sump Blaze Logic Analyzer symbol to see the relevant code... It's probably better to look at the commits I made to github to really see what is going on. The other thing is that all of the VHDL work is working well as I remember, the work that needs to be completed is the C++ code, but the VHDL is all working just fine.

I've been digging into FuseSOC, which was recommended in this thread, and I'm liking what I see so far. I think it will be much easier to create a project to direct you to that just has the relevant code at the top level with FuseSOC.

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Jack,

I can deal with any firmware issues since I have been coding low-level firmware professionally for decades.  I am just having trouble with figuring out how I can write VHDL code that writes to the wishbone interface that the firmware can then read.  To me, this would be the most powerful feature of your environment over straight VHDL, since one could use VHDL for things that firmware is not fast enough to handle, and use firmware for manipulating the data that the VHDL code sends to it at a more leisurely pace.  I see how it is done in the schematic, but I find the schematic a hindrance (kind of like these visual programming languages that kids use on Mindstorms), and  would really much rather just deal with VHDL.

I wasn't aware that "edit circuit" was doing something besides just calling ISE.  If you could help me solve this issue and that would allow me to compile the logic analyzer code in the ISE environment (which I am comfortable with), I would be very grateful.  My development environment is Lubuntu 14.04 (I have other computers on 16.04, but since your development environment came out before 16.04, I didn't want to risk incompatibilities and deal with trying to get another license from Xilinx).  I installed DesignLab and ISE on Windows 7 to see if this was a Linux issue, but from what I remember, I had even worse problems on Windows 7 (I don't have that computer with me, so I don't remember exactly what the issues were).

As further comments on your back to basics, I would think it would be very useful if your site had more VHDL examples that were ported to your hardware, with lots of comments.  Hamster has (or had since I read on it that he was going to take it down) a site with tons of examples, but many are for other boards, and the explanations are rather terse.  Most of the examples on your site now start out with Arduino code, and then bolt some pre-written schematic code on, and also require the compute or game shield/wing (I only have the logicstart shield/wing).  I know you have some tutorials on how to modify the schematics, but I would rather just cut to the chase and deal with VHDL.

Don't get me wrong, I think your site is much better than any of the other FPGA sites that I have seen, and greatly appreciate all the effort you have put in, but when I run into trouble with DesignLab, I can't just search the web for answers like I do for everything else, and I haven't been able to find the answers in your examples, forum, and learning site.

Blake

 

 

 

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Jack,

When I click on "edit circuit" today, it doesn't hang (maybe because I launched it from the command line the first time instead of just clicking on it in the GUI).  The attached screenshot shows what I see.  Can you explain to me how I "push into the Sump Blaze Logic Analyzer symbol to see the relevant code".

Blake

2017-09-24-072841_1440x900_scrot.png

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Jack,

I figured out how to "push into" BENCH_wb_SumpBlaze_LogicAnalyzer32, which allows me to see BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd.  Is there a way to see all the vhdl files in the circuit, and recompile it like a normal .xise project, which would could then be loaded by DesignLab?

Blake

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You can see all of the files for the project on the left side under the hierarchy side. Start from the top level which is an icon of a tree with a green box at the top. 

To generate the bit file just double click "Generate Programming File" under the Processes section.

This tutorial walks you through what you need:

http://gadgetfactory.net/learn/2015/05/08/designlab-editing-a-zpuino-system-on-chip-circuit-2/#Synthesizing_the_circuit

Jack.

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7 hours ago, bnusbick said:

 

I can deal with any firmware issues since I have been coding low-level firmware professionally for decades.  I am just having trouble with figuring out how I can write VHDL code that writes to the wishbone interface that the firmware can then read.  

Hi Blake, from all your questions, like the one above it is obvious that you just struggle with the basic concepts of modeling hardware with VHDL.

Writing HDL Code that is writing or reading data over a wishbone interface requires first to understand the wishbone protocol (search for Wishbone B4 spec on the internet), and then understanding the concept of building a finite state machine in VHDL. This is not so different from doing a state machine in software.

There is some literature on doing so. A free ebook describing this and other concepts is for example Free Range VHDL eBook.

The book is a good entry into VHDL, although it always stay on the abstract level and not discuss technology mapping. 

Closer to Xilinx FPGAs is „FPGA now what“ from XESS Corp. Albeit referencing their FPGA boards (The XuLa series) it is largely appicable for all Xilinx FPGAs. It also describes the workflows with ISE. 

Another good book for Xilinx FPGAs is „FPGA prototyping by VHDL examples“, the spartan 3 version can be downloaded for free http://onlinelibrary.wiley.com/book/10.1002/9780470231630

Most of the concepts still apply for newer FPGAs.

When you are familiar with the basics, and have understood things like Clock Managers and .ucf constraint files it is also not so complicated to adapt code to other boards. Than also Hamsters examples are understandable without additional comments.

In addition you can download Xilinx guides, like the „XST users guide“, it contains code patterns do infer things like block RAMs, DSP blocks , etc. It may also be helpful to download data sheets of the other chips on the FPGA board. When for example if want to integrate Hamsters SDRAM controller into a design, it makes sense do understand how a SDRAM works.

Thomas

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Hi Jack (and everyone else),

first of all, two thumbs up on your effort to make FPGA development easier. I'd like to throw in my two cents since I think the approach isn't quite getting near an "Arduino for FPGA", which seems to be the goal.

The Arduino has an extemely low barrier to entry, which the Papilio is missing. Some time ago me and some colleagues took an Arduino and built some cool stuff within minutes, despite me having never worked with a microcontroller. Download the IDE, copy&paste an example from the net, run it, modify a few things, run again -- there it is, the first blinking-LED program I built on my own. Everyone was enthusiatic about it.

Contrast that with the up-front effort needed to do the same with an FPGA. I tried to bring an FPGA into the mix the same day, just for fun, and we gave up before we finished installing ISE. Despite me having build a CPU clone in Verilog before, so it was definitely not lack of skill. Despite the Verilog code for a few blinking LEDs is no more complex than doing the same in C. Despite the others being programmers who, even without experience in hardware, would have grasped the way Verilog works easily. It was just the artificial barrier to entry that was too high compared to Arduino: get an ISE license (on some unmaintained legacy licensing site), download ISE (way too big), install ISE (doesn't run on MacOS X), use ISE (I hope the guys who built that got fired).

My take is to start with the premise that the barrier to entry must be as low as for Arduino. That likely means to remove ISE from the loop -- even with a cloud-hosted version, asking people to register on the Xilinx homepage and obtain a license file just for the sake of it is exactly what should NOT happen.

Without ISE, things are obviously getting harder. The most obvious approach would be to build a (large!) series of "batteries included" FPGA configurations, synthesize yourself in ISE (or command-line xst, ngdbuild, par, bitgen), and make them available as bitstream files. Then, just like now, let the user select one of pre-built bitstream files and write software for it. This is not VHDL development, but offering a large number of pre-built FPGA configurations comes closer. Building these from common code can be done in scripted builds.

The next step would be to make large parts of these configurations run-time configurable through (Verilog-defined) programmed registers, BlockRAM contents, etc. This gets even closer to hardware design. Except for the high-performance stuff, most parts don't mind including yet another mux to make the design more flexible. 

As a further tool, these "soft" configuration parts can be patched into an existing bitstream. The locations of BlockRAM and LUT contents are well-known enough to do that.

Again, just my opinion.

 

Greetings,

Martin

 

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Thomas,

Thank you for the suggestions.  I will look into them.

Jack,

Thank you for showing me how to build the bit files.  When I do this, I get the following errors:   

  Parsing architecture <behavioral> of entity <benchy_wb_sumpblaze_logicanalyzer32>.
   ERROR:HDLCompiler:1314 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd" Line 143: Formal port/generic <run> is not declared in <core>
   ERROR:HDLCompiler:432 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd" Line 129: Formal <exttriggerin> has no actual or default value.
   INFO:HDLCompiler:1408 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Benchy/core.vhd" Line 55. exttriggerin is declared here
   ERROR:HDLCompiler:854 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd" Line 49: Unit <behavioral> ignored due to previous errors. 
   VHDL file /home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd ignored due to errors
 

As Thomas correctly points out, I will never get the hang of this until I put in the time to truly understand ISE, VHDL, and what is necessary to map this to the Papilio boards, so I will try to resolve these errors by myself.

However, as Martin points, out, there are lots of very bright people who are not willing to go through all this just to see what FPGAs are all about.

Blake

 

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1 hour ago, Martin Geisse said:

 

Contrast that with the up-front effort needed to do the same with an FPGA. I tried to bring an FPGA into the mix the same day, just for fun, and we gave up before we finished installing ISE. Despite me having build a CPU clone in Verilog before, so it was definitely not lack of skill. Despite the Verilog code for a few blinking LEDs is no more complex than doing the same in C. Despite the others being programmers who, even without experience in hardware, would have grasped the way Verilog works easily. It was just the artificial barrier to entry that was too high compared to Arduino: get an ISE license (on some unmaintained legacy licensing site), download ISE (way too big), install ISE (doesn't run on MacOS X), use ISE (I hope the guys who built that got fired).

OK, ISE is quite large and not the most user friendly (which is in my opinion also true for the "number one" IDE in general - Eclipse). But it is not really complicated to install. To blame Xilinx that does not run on MacOS X is a bit unfair, given the market share of Macs in typical hardware labs. ISE and Vivado run very well on Linux. Also getting a Web Pack license is not that complicated. When I started with the Papilio I got the example in Hamsters tutorial  running after half a day, and this included the dirty hack required to get ISE running with Windows 10.

FPGAs a very complex devices and synthesis of VHDL/Verilog to the FPGA hardware is much more complicated than writing a software compiler. For such I have great respect for people building such tools and don't agree with you blaming them. 

I also think that FPGAs will never be as easy and popular as Arduino, etc, but this not because of the tools, it is caused by the very concept.

There are simple mucher fewer use cases for a FPGA instead of a MCU it will justify the effort (time and cost) of using a FPGA. Most things can be done easier in software, if it is to slow, in many cases you can just switch to a more powerful board to solve that problem. So I think "hobby" FPGA is limited to people like me, who are interested in the topic itself and wan't do design hardware.  It was always my dream to design a processor and now I can do it. Does it make sense in an economical way? Of course not, my $100 FPGA board cannot do more than $20 (or even cheaper) board with some ARM Cortex-M clone.  My real "productive" MCU applications (like telemetry sensors for RC model airplanes - my "other" hobby") are all done with Arduino mini boards. The have just a more convenient form factor...

 

2 hours ago, Martin Geisse said:

My take is to start with the premise that the barrier to entry must be as low as for Arduino. That likely means to remove ISE from the loop -- even with a cloud-hosted version, asking people to register on the Xilinx homepage and obtain a license file just for the sake of it is exactly what should NOT happen

This is unfortunately not possible because the vendors document FPGAs in a way that it can be programmed without their tools. There is one exception:  The project IceStrom from Clifford Wolf:http://www.clifford.at/icestorm/

He reverse engineered a specific FPGA family from Lattice Semiconductor and build a complete open source toolchain for it. Such a toolchain could be installed in a freely distributed VM or cloud solution. But I have no idea how long the iCE40 FPGAs will stay on the market. The release of IceStorm at least led to a high demand of the respective evaluation boards and out-of-stock situations. The iCE40 are also quite small,  IceStorm only supports Verilog and no VHDL, the tools are also much less mature and user friendly than commercial too chains from the vendors. So for the moment I will stay with ISE and Vivado (for the newer Xilinx FPGAs).

2 hours ago, Martin Geisse said:

The most obvious approach would be to build a (large!) series of "batteries included" FPGA configurations, synthesize yourself in ISE (or command-line xst, ngdbuild, par, bitgen), and make them available as bitstream files.

I cannot imagine that this makes any sense, to be honest. One of the advantages of FPGAs over a "fixed function" MCU is that you don't need to build in things you do not use. So instead of trying to understand some crazy complex I/O controller on an MCU I just create one in VHDL which has exactly the functionality I require. 

 

2 hours ago, Martin Geisse said:

Except for the high-performance stuff, most parts don't mind including yet another mux to make the design more flexible. 

Muxes are the performance killer number one on FPGAs to my experience. 

2 hours ago, Martin Geisse said:

As a further tool, these "soft" configuration parts can be patched into an existing bitstream. The locations of BlockRAM and LUT contents are well-known enough to do that.

For Block RAM I agree (Xilinx data2mem is exactly doing this). But for LUTs it does not make sense. Even if it is possible, the mapping can dramatically change with small deviations in the design. Of course it is possible to do manual technology mapping and instantiate LUTs with respective macros. There is one crazy guy doing this with a complete processor btw...

But to be honest, making all this complicated things which as consequence makes it impossible to write your design as clean, readable and portable VHDL/Verilog coding just to avoid installing a tool and a license key is ridiculous.

It is good practice in HDL design to rely on inference as much as possible instead of instantiation. 

 

Thomas

 

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15 minutes ago, Thomas Hornschuh said:

OK, ISE is quite large and not the most user friendly (which is in my opinion also true for the "number one" IDE in general - Eclipse). But it is not really complicated to install. To blame Xilinx that does not run on MacOS X is a bit unfair, given the market share of Macs in typical hardware labs. ISE and Vivado run very well on Linux. Also getting a Web Pack license is not that complicated. When I started with the Papilio I got the example in Hamsters tutorial  running after half a day, and this included the dirty hack required to get ISE running with Windows 10.

That's exactly my point. The time required to get a simple tutorial to work with Arduino is not half a day plus a dirty hack, it's more like ten to twenty minutes and works out of the box.

 

Quote

I also think that FPGAs will never be as easy and popular as Arduino, etc, but this not because of the tools, it is caused by the very concept.

The concepts are indeed harder than software, but not at all as bad as usually described. In fact, the quality of the tools (such as bad error messages) contribute a lot to it. Try programming C with a compiler that outputs useless messages instead of GCC.

 

Quote

Muxes are the performance killer number one on FPGAs to my experience. 

That's fine in many cases where performance is not your primary concern. The Arduino isn't exactly a candidate for high-performance computing either.

Take for example a pin that could be a loadable output, PWM or delta-sigma, serial port (shift register), and so on. Another mux in that path doesn't matter because none of that is time-critical down to a single clock cycle.

The really critical parts are things like Ethernet, video signal and memory controllers. These tend to be fixed paths on the PCB for the same reason and thus could be hardcoded in a board-specific configuration, which is written once and compiled the traditional way (xst, ngdbuild, par, bitgen).

 

In the end, most of what you say comes down to goals and priorities. My comment was aimed at Papilio being a competitor to Arduino for special-case applications where an MCU doesn't cut it. Most of what you say more applies to the design of a traditional FPGA development board.

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Taking ISE out of the loop would make the whole thing pointless though. It's an FPGA, it's never going to be *as simple* as an Arduino, the complexity is part of what makes it so powerful. There could never be enough pre-compiled bitfiles to support even a fraction of the projects out there and it would end up just another MIST/Minimig/Chameleon/Replay etc. Trying to bypass the entire development process would bypass the whole point of using an FPGA and prevent even more people from taking the time to learn. Sure ISE is not the most user friendly software out there but you have to remember that it's a complex professional tool. AutoCAD, Photoshop, 3DS Max, Altium, and other high end professional tools are also not known for being particularly user friendly but that's the price to pay for they power and versatility they offer. The licensing I agree is a bit of a pain but at least it's available for free and if dealing with Xilinx is too much trouble there are "other" places you can acquire ISE and/or a license file if you look around. A few years ago at least Xilinx would send you a free DVD if you requested, I still have one here that I use when I need to install it. Yes the download is large but with a little planning ahead it's no big deal, order your FPGA board then go start the download and go do something else. In some time it will be done and then while you wait for the hardware to arrive you can install it and familiarize yourself with the tool. It would not hurt to have a few more ready to use example projects out there but there's no point in trying to cover all bases.

 

I wonder if a DVD-R of the ISE installer could legally be included with the Papilio boards? Depending on the volume, the cost and overhead to provide that would be relatively low, maybe offer it as an option during ordering for a small fee to cover the cost of the disc.

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On 9/22/2017 at 6:07 PM, Thomas Hornschuh said:

I think the problem with Wings is similar to Arduino shields:  They almost never fit. Either something needed is missing, or there is something unneeded which occupy I/O pins which may be needed for other purposes. I did some work with Arduinos but never bought a shield. I often buy small breakout boards for a single purpose, e.g. sensor boards, realtime clocks, etc. 

Thomas

 

That's a good point. I use the Logicstart megawing quite a bit but I do wish it had a microSD card slot instead of the ADC which I've never used. If it did though someone else would be wishing it had an ADC instead of a micro SD slot. The individual wings are perhaps more versatile, however for stuff that simple I tend to just breadboard it or use various little breakout modules from China and connect them with jumper leads. I suppose what that comes down to is it's just really hard to compete with China.

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Just a quick note: Adding ZPUino support for AMBA/APB/AHB[-lite]/AXI is not that difficult, although we may not be 100% compliant in the first stages, due to split address+data phases on some of these protocols - still, mapping between the classic wishbone to APB and pipelined wishbone to AHB-lite should be fairly straightforward.

If that eases integration with Vivado, we may as well just move to AMBA buses from the ground up.

Alvie

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6 hours ago, alvieboy said:

Just a quick note: Adding ZPUino support for AMBA/APB/AHB[-lite]/AXI is not that difficult, although we may not be 100% compliant in the first stages, due to split address+data phases on some of these protocols - still, mapping between the classic wishbone to APB and pipelined wishbone to AHB-lite should be fairly straightforward.

If that eases integration with Vivado, we may as well just move to AMBA buses from the ground up.

Alvie

Hi,

actually converting Wishbone to axi4 on the master side is quite easy. To write an AXI4 slave supporting all the bell and wristles may be hard, but the master require only support what it needs. When porting Bonfire to Vivado/Arty I build two simple Wishbone to AXI4 bridges. Now the toplevel of Bonfire is more or less compatible to Microblaze, it has an IC (Instruction Cache) and DC (Data Cahe) master which is burst capable, and a DP AXI4Lite port for peripherals. 

The both bridges (see attachments) are nearly identical, that could be combined to one with generics. But because AXI4Lite has much less signals I decided to keep them separate for convenience. A better solution may be to make axi4lite as a wrapper to axi4. The bridges collapse to around 10 LUTs when Vivado optimizes the design.

They are just fitted to my requirements, support of AXI4 Burst transactions requires also Wishbone Burst support. On the other hand it don't support pipelined mode yet. Maybe you remember our discussion a while ago about the different bus implementation of ZPUIno vs. Bonfire.  

The bridges passed a run to Xilinx axi verification IP, so there protocol implementation is "correct". Nevertheless they are not very bulletproof yet, when master or slave prematurely abort a burst behavior is not defined. Also you need to make sure that the bridge and the Wishbone master use the same burst size.

The nice part about AXI with Vivado is, that you can easily use  the Xilinx Cores (like e.g. the Ethernet controller). And you can use the AXI Smartconnect, this is a universal bus connect which almost automatically adapt to the situation. It can for example convert between AXI4 and AXI4Lite, it can convert bursts to devices not supporting bursts, it can adapt to different bus widths and can cross clock domains and much more. 

Of course it is far away from the open source idea. But as long as we need to use the proprietary tools of the vendors anyway, why not use things that makes live easier from time to time :)

Thomas

wishbone_to_axi4lite.vhd

wishbone_to_axi4.vhd

Edited by Thomas Hornschuh
Typos

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5 hours ago, Martin Geisse said:

That's exactly my point. The time required to get a simple tutorial to work with Arduino is not half a day plus a dirty hack, it's more like ten to twenty minutes and works out of the box.

 

If this really makes the difference for somebody I think he has not enough patience for software or hardware development :)

With Arduino everything is easy as long as you write small programs and can work with the polling model the Arduino libs. If you need to do something special (e.g writing interrupt handlers) you have to read Atmel manuals and doing all sorts of low level stuff. Also dealing with PROGMEM attributes, etc. Arduino tries to draw a nice simplified picture over MCU programming, it even tries to hide that it is C++ and give people that it is some user friendly beginners language. But immediately below this surface are lying all that pitfalls. I know it quite well, because I once published an Arduino Library for a RC equipment telemetry bus popular in Germany. It has now about 100 downloads and despite I tried to make it easy to use, from the feedback I get I would assume that only about half of the downloaders are able to successfully finish a application with it. Some of them are not even able to run the example. And only a very small fraction is on a level that they would understand the library and modify it. 

And given the tools, gcc may give better error messages than ISE, but with standard Arduino there is no possibility to debug code. In this sense Arduino (at least on the ATMEGAs) suffers from the same problem than the FPGA topic: The "professional" tools are proprietary and sometimes need expensive equipment from the Vendor.

Nevertheless Arduino creates a great value in providing at least the easy entry: As starter you don't have to worry about JTAG adpaters, Fuse programming, and the hardware registers. You can start with what Arduino provides out of the box and then grow into as you go further. It just softens the "bare metal" experience of a raw ATMEGA or similar MCU. Indeed I found this also very helpful, having many years of development experience including systems programming, but never used a MCU before. 

But my experience with the Papilio Pro was equally positive. On the other hand the world has changed, the larger vendors like Digilent or Avnet became aware of a the "maker and hobbyist" market segment and came out with products where people like Jack will have a hard time to compete. With the proper board support packages you can  connect I/O, memory and processing cores together to a system and then export the design to SDK and write the software on top of it.
To use the DDR3 RAM on the board you don't need to read the 200 pages "Xiling Memory Interface generator" manual. Just move the RAM from the board view to IP Integrator. It sets up a MIG with the right parameters for the chip soldered to the board, you don't even  need to edit a constraint file, this all works automatically. 

 

6 hours ago, Martin Geisse said:

My comment was aimed at Papilio being a competitor to Arduino for special-case applications where an MCU doesn't cut it. Most of what you say more applies to the design of a traditional FPGA development board.

I think what Arduino has done to the industry is the "consumeration" of embedded electronics products. Vendors publish their official evaluation boards in Arduino form factor.  "Professional" toolsets are equiped with Arduino compatible libraries.  So I don't see the difference you mention. Is the Digilent Arty series (there are three boards in the meantime) a "FPGA evlaution board" or an "Arduino with a Soft SOC implemented in a FPGA?

Thomas

 

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Quote

If this really makes the difference for somebody I think he has not enough patience for software or hardware development :) (...)

The same discussion has been there for Arduino, and I don't think there is value in repeating it here. Nevertheless, Papilio seems to present itself as an "Arduino for FPGA", so whether or not you like the Arduino approach, I think Papilio is currently not quite reaching that goal. 

 

Quote

But my experience with the Papilio Pro was equally positive. On the other hand the world has changed, the larger vendors like Digilent or Avnet became aware of a the "maker and hobbyist" market segment and came out with products where people like Jack will have a hard time to compete. With the proper board support packages you can  connect I/O, memory and processing cores together to a system and then export the design to SDK and write the software on top of it. To use the DDR3 RAM on the board you don't need to read the 200 pages "Xiling Memory Interface generator" manual. Just move the RAM from the board view to IP Integrator. It sets up a MIG with the right parameters for the chip soldered to the board, you don't even  need to edit a constraint file, this all works automatically. 

I would be surprised if all that works without downloading gigabytes of IDE and jumping through hoops to get a license file...

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To summarize, I think that within the constraints of FPGA development I've gotten as close to being the Arduino of FPGA's as is possible. The things that I'm hearing people say they want, a library of premade bit files, examples that just work out of the box, and not having to deal with Xilinx ISE to use an FGPA. Those are all there and work, you just have to download DesignLab and you don't need the Xilinx ISE to be using premade bit files, tons of examples, and do advanced things like changing the functionality of a pin to do something else. With a download that is exactly the same size and as easy to install as the Arduino IDE you can do a ton of things with the Papilio FPGA. It's when you want to start editing the bit files and changing the functionality of the bit files that you need the Xilinx ISE. There is nothing that I or anyone else can do about that, its just how FGPA vendors operate. What Alvie and I were trying to accomplish was make FPGA's more accessible to people which I think we did. Where else can you download ready to run SOC designs for an FPGA that does all of the following without ever downloading a license file or installing the huge Xilinx ISE IDE:

  • VGA output with multiple examples like a brick game and jet set willy
  • multiple classic audio chips
  • a ready to go logic analyzer
  • ability to drive an RGB LED Matrix panel
  • play video games with the gameduino core
  • a waveform generator
  • bitcoin miner

All of these projects work with a simple 300MB download of the DesignLab IDE. 

So to say:

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Nevertheless, Papilio seems to present itself as an "Arduino for FPGA", so whether or not you like the Arduino approach, I think Papilio is currently not quite reaching that goal. 

Discounts what DesignLab does provide and what we have accomplished. It's probably as good as anyone can get to making a Xilinx FPGA do more then blink a LED in 15 minutes.

The work we have done is meant to make FPGA's accessible and able to do useful things out of the box for the Arduino crowd. I think DesignLab without downloading ISE does that very nicely, but I think the people who are disappointed have not truly even used that functionality and are really coming from the angle of wanting FPGA circuit design to be easier. That is something we have certainly not accomplished.

I put a lot of time and effort into trying to accomplish this using the schematic editor and that is what I feel has not been successful. In large part because of the problems also described here such as the huge download and the huge hassle of dealing with their licensing system. These problems are completely out of our control and not solvable by us or anyone else other then the vendors... Certainly not with the resources I have available.

What I can do going forward is to get away from the schematic based approach, because it is not serving anyone well, and get to work on a library of VHDL/Verilog libraries and projects for the people who really want to come at this from the circuit design side of things. I'm not going to worry about trying to make it easier, people will have to learn VHDL/Verilog on their own, but hopefully providing ready to go and proven libraries that work on the Papilio board will be more valuable to end users then premade bit files in Designlab has been. 

If I can come up with a cloud based IDE solution that takes care of the install problem then that is going to be great. But there is nothing I can do about the licensing problem...

Cheers,

Jack.

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11 hours ago, Jack Gassett said:

The work we have done is meant to make FPGA's accessible and able to do useful things out of the box for the Arduino crowd. I think DesignLab without downloading ISE does that very nicely, but I think the people who are disappointed have not truly even used that functionality and are really coming from the angle of wanting FPGA circuit design to be easier. That is something we have certainly not accomplished.

Hi Jack,

maybe the disappointment is caused by your "advertising" (e.g. Videos) could be misleading it shows simple "draw your circuits" examples. But in this discussion here are two guys expressing their disappointment? Are they representative? 

I must confess that I never downloaded Designlab, it was just not a fit for my requirements. Nevertheless, and I repeat myself, your products and your website are a great starting point for FPGAs. 

I think you have some bias on retro computing, which is not that bad, because retro computing projects also are a good starting point for digging deeper into the FPGA topic. Legacy technology is just better accessible. VGA and PS/2 is much easier to understand and implement than HDMI and USB for example. 

I think also ZPUIno is great, because it is a complete open source SoC with a clear system architecture.  

And given the example of Vivado IP integrator, schematic entry as tool for building a system from ready-to-integrate IP cores is not the wrong way. You just tried it with inappropriate tools :)

12 hours ago, Jack Gassett said:

I'm not going to worry about trying to make it easier, people will have to learn VHDL/Verilog on their own, but hopefully providing ready to go and proven libraries that work on the Papilio board will be more valuable to end users then premade bit files in Designlab has been.

100% Agree. Maybe consider it to be independent of Papilio, this may open your work to a greater audience. 

Thomas

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