james1095 Posted August 21, 2017 Report Share Posted August 21, 2017 I've recently been playing with a TFT screen that has a plain RGB dot clock interface and got it working with a couple of the arcade games. I have a few small TFT displays that are capable of interfacing with the same method but they require initializing via the SPI interface to configure them to enable the RGB interface. One uses the SSD2119 chipset and a couple others are various ILI9xxx chipsets, all of which work similarly. Have any of you used one of these displays? I'm looking for a chunk of VHDL (ideally, but Verilog would work in a pinch) that will spit out a series of commands to initialize the display, anyone got something that already works? This seems like the sort of thing that would be out there but I haven't quite found what I'm looking for. Quote Link to comment Share on other sites More sharing options...
vlait Posted August 25, 2017 Report Share Posted August 25, 2017 For the ILI chips you could probably adapt https://github.com/thekroko/ili9341_fpga or yomboprime's yombotft addon for zxuno (also on github) The ILI datasheet also has the info, although in a little less understandable format. br, -V Quote Link to comment Share on other sites More sharing options...
james1095 Posted August 25, 2017 Author Report Share Posted August 25, 2017 Thanks, I actually came across that link the other day and thought I'd give it a try. Unfortunately it's in Verilog but I picked up a ILI9341 based display and figured I'd try to get the example working. Once that's done I can translate it to VHDL and then attempt to modify it for the other displays. Those TFT controller datasheets have a lot of information but I found it difficult to find good info on just what needs to happen to initialize the display. Quote Link to comment Share on other sites More sharing options...
james1095 Posted September 18, 2017 Author Report Share Posted September 18, 2017 After playing around with this a bit I've decided to translate it to VHDL so it's easier for me to work with. Most of it is pretty straightforward but a couple of the lines I'm not entirely sure what they do. Could one of the resident Verilog experts explain exactly what these two lines of code do? The second one I suspect is assigning cs <= '0' when internalSck is true but I'm not certain. idle <= &counter; if (internalSck) cs <= 1'b0; Quote Link to comment Share on other sites More sharing options...
mkarlsson Posted September 18, 2017 Report Share Posted September 18, 2017 46 minutes ago, james1095 said: idle <= &counter; idle is set to 1 if all bits in counter are 1 (unary reduction operator AND) 50 minutes ago, james1095 said: if (internalSck) cs <= 1'b0; if internalSck is high then cs is set to 0 Quote Link to comment Share on other sites More sharing options...
james1095 Posted September 18, 2017 Author Report Share Posted September 18, 2017 Perfect, thanks! So I had the second one right, the first one I had no idea but it makes sense now that I see it explained. The problem I've had with this sort of thing is trying to search for explanation I can't just google the line of code because the signal names are arbitrary. One of these days I should probably learn Verilog too but it's hard enough to be proficient in just one language without taking on a second one. Quote Link to comment Share on other sites More sharing options...
mkarlsson Posted September 18, 2017 Report Share Posted September 18, 2017 For a more detailed description of the first line see https://www.nandland.com/verilog/examples/example-reduction-operators.html Magnus Quote Link to comment Share on other sites More sharing options...
vaibhav.m Posted August 31, 2019 Report Share Posted August 31, 2019 Can you pls share your progress if you were successful in integrating them ?? Quote Link to comment Share on other sites More sharing options...
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