danirebollo

ZPUINO on custom board (Spartan 3)

14 posts in this topic

Hi everyone,

I have a papilio pro working successfully with designlab but I want to use a custom board (like papilio one) with it. I've selected papilio one 250k and "Load circuit" seems to be ok, but when I tried to upload... the output is attached:

"Cannot get programmer version, aborting". 

I've checked COM port, FTDI configuration EEPROM is empty (with FT_prog), papilio drivers are loaded... I also tried to change some values in the FPGA (HSWAP is '0' so every pin will be pullup, but I've pulled up M0 and M2, and M1 to GND. Also "Done" and "init b" pulled up.)...

Any help?

My XC3S250E has different IDCODE so I've added this line to the devlist.txt file:

Quote

11C1A093        6       XC3S250E

Papilio-prog seems to work good.

What is the problem?

 

Thanks

qq.JPG

qw.JPG

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Does your board have a "DONE" LED or pin so you can check if the FPGA starts ?
Are FTDI/Serial connections the same as in original ?

Why does your FPGA have a different ID code ?

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Thanks for your reply,

I will try to check DONE signal right now, but in the origilal papilio one design DONE is floating, while Spartan3 datasheet says will be pulled up with 330R. I've tryed both ways.

FTDI/serial are the same. but I use a buffer between JTAG signals.

I dont know why ID code is different... I dont know if this code is related to a FPGA model or production date or another thing... But It is from china factory. Maybe counterfeit or baf FPGA from production, but the think is: The FPGA works. Both ISE and papilio-prog, and also xc3sprog, works without problems.

456.png

1234.JPG

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Can you try swapping TXD/RXD in the UCF file ? I recall we had some "misunderstanding" regarding the TX/RX direction. That was a long time ago, though.

Alvie

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Oh I just realized the papilio one have XC3S250E-VQ100 and my board XC3S250E-4TQG144C... But I think I've seen some TQG144G.. maybe I'm confusing myself with papilio pro. Anyway.. ¿how to change the configuration file into the designlab?

Edit:

I've found: DesignLab-1.0.8\examples\00.Papilio_Schematic_Library\Libraries\ZPUino_1\PSL_Papilio_One_250K\papilio_one.ucf 
If I modify only this file it will be ok? (I dont know how designlab call ISE and if there is snother configuration file...)

Thanks

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I'm trying to recompile adding some files to the project because lost links and now the error is caused by ZPUino_Papilio_One_V2_blackbox.ngc, cause ISE says it is for Spartan3 VQ100 only.

What is this core and why it is blackboxed?

11a.JPG

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Hello,

It's black boxed because it greatly speeds up the synthesis time for the end user and most people have no need to modify ZPUino, just the peripherals attached to it.

The source code for the black box is here:

https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuino/boards/papilio_one/s3e250/variants/designlab

Jack.

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Oh thank you,

I will try to recompile. I've also recompiled the bscan spi file with my constraints. I have an error trying to program the spi even with papilio prog and xc3sprog (with the fixed bscan)... I dont know why... 

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16 hours ago, Jack Gassett said:

Hello,

It's black boxed because it greatly speeds up the synthesis time for the end user and most people have no need to modify ZPUino, just the peripherals attached to it.

The source code for the black box is here:

https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/hdl/zpuino/boards/papilio_one/s3e250/variants/designlab

Jack.

It is a Xilinx project?

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Yes, it's a Xilinx project. You may merge all sources into your own project if you like. However blackboxing the core (which is almost always the same) will decrease synthesis time significantly.

Alvie

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Yes, it's a Xilinx project. You may merge all sources into your own project if you like. However blackboxing the core (which is almost always the same) will decrease synthesis time significantly.

Alvie

You need to use make to synthesize the project.

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13 minutes ago, Jack Gassett said:

You need to use make to synthesize the project.

I need to update that project file...
I do have a script able to generate the .xise file from the main Makefile/prj. However links are broken since I moved stuff around.

Will do ASAP... and fix all variants in the way (I did update the main project/boards ones, not all variants though).

Alvie

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I fixed paths (not yet on master) and generated a ZIP export file. Should work... not sure - fails on my side with:
 

INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - 

   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. 

Care to try ? Your luck may vary...

Alvie

ZPUino_Papilio_One_250K_V2_blackbox_dist.zip

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