Multicore Architecture Design with Papilio Pro

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I would like to design a multicore architecture using three MicroBlaze softcore(s) which are connected together using FIFO channels and also connected to the shared memory (DDR-RAM) as presented in the attachment.

My question is if I can design the same architecture using Papilio as I've designed it on Genesys Virtex 5 using Xilinx EDK. If yes, which Papilio board should I buy?



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Don't think it would fit any of the Papilio boards. Perhaps the big Pipistrello, have a chat with Magnus ( @mkarlsson ), he should know better than I do (and he uses Microblaze often).


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you could check Trenz TE0725 with Artix 7 up to -100 size. I once had a Microblaze on one of them (was replaced later in the design cycle) and it definitely utilized less than 1/3 of resources. You'll want the Digilent-licensed "XMOD-FTDI" adapter to use the debugger (no idea how hard it is to set up with multiple targets, there is one JTAG option USER1-4 in the MB config that might be relevant). There is a 1.8 V variant, most likely 3.3 V is the better choice. To put it into perspective, it's probably 2x...3x the price of a Papilio.

With Vivado on Artix I think you have more microblaze configuration options than on Spartan with ISE.

Note: I'm not aware of any ready-made solution to access the memory module on that board. For the Papilios there are soft memory controllers, and Pipistrelly can use the hardware core that's bonded out on the larger FPGA sizes.
And, for Spartan 6 there is some community but I haven't found that yet for Artix...



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