Luís Marques

D/DHDL + Classic Empire on Papilio Pro

6 posts in this topic

Hello,

I've just returned from DConf 2017, in Berlin. There I gave a talk on how to use an extension of the D programming language (DHDL) to design hardware. I showed a demo of Classic Empire, a game written by Walter Bright (the original creator of D), running on a Papilio Pro, inside a soft-core RISC-V CPU, plus my own handmade "wing" IO accessories and respective controller IP blocks (VGA, 7-segment, sound, etc.). You can see a quick demo below:

You can also see the full talk, if it sparks your interest:

Thanks to the generosity of GadgetFactory, we raffled a Papilio Pro and some accessories to the participants of the talk:

Gauging from his reaction, Vang Le was very surprised and happy to be the winner, and he's looking forward to exploring the world of FPGAs.

In my demo I loaded the binary code for the game through the USB/UART, using a custom utility. In the next few months I plan to further tweak this demo, so that the game code is loaded from flash and it works with standard GadgetFactory wings. When that is done, I'll provide the bit stream files for the combined hardware design + the game. Walter Bright has indicated that he would provide permission for the FPGA version of the game to be distributed freely, so GadgetFactory could use it for its showcase. Later, I will provide the source code for my whole setup; I used the LDC 2 D compiler with the (old) LLVM RISC-V backend, and I had to workaround a lot of bugs of invalid RISC-V code. When the new LLVM RISC-V backend is released I expect all of that to be alleviated or completely fixed, which will help with the release of the complete demo setup.

I'll keep providing updates and feedback here on the GadgetFactory forums. You can also follow me on Twitter (@Luis3m), or email me if you have any questions (http://www.luismarques.eu/about).

Also, a shout-out goes to Mike Field, whose book / tutorial helped me get started with FPGAs and hardware design. I shared the love for his book with some conference participants :-)

So long,
Luís

 

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I read one of your PDF files, and to be honest I have much more questions now than I had before, like:

- How do you model different clock domains ?

- How do you integrate with hard-IP blocks ?

- How do you model multi-cycle operations, like a 5-pipeline multiplier ?

If you happen to come by Coimbra you may explain me these in more detail :)

Alvie

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32 minutes ago, alvieboy said:

I read one of your PDF files, and to be honest I have much more questions now than I had before, like:

- How do you model different clock domains ?

- How do you integrate with hard-IP blocks ?

- How do you model multi-cycle operations, like a 5-pipeline multiplier ?

If you happen to come by Coimbra you may explain me these in more detail :)

Alvie

- The circuits have an implicit clock, but you can specify your own input clock ports and assign those clocks to sub-circuits. Synchronization between those clocks domains is done manually;

- You can integrate external Verilog / VHDL modules, so if your hard-IP blocks can be instantiated from Verilog / VHDL then you just instantiate one of those;

- At its most basic, you manually instantiate the stages and registers that connect the various stages, just like in Verilog / VHDL. It should be possible to create higher-level abstractions based on that, but I haven't explored that yet. If you mean how do you use the times ("*") operator and automatically get a multi-cycle multiplier, you can't do that, not at the moment, you'll have to manually create a multiplier. Of course, you can design a generic/parameterised multiplier once and be done with that. You get more flexibility for creating generic components than with Verilog / VHDL, whose introspection abilities are a bit limited.

You're from Coimbra? Yeah, we can meet there some time, or whenever you come to Lisbon :-)

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Thanks for your reply, Luís. Yes, I am from Coimbra, but don't go to Lisbon that often (except to fly abroad, and that's more often that I'd wished).

Still one question: how do you model sync vs. async resets ? Rather easy in low-level HDL languages, but hard to do even in SystemC (I heard newer versions do support it, but it's an ugly hack in my opinion).

Alvie

 

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The reset behavior is automatically generated by the tools; you can choose from a predefined list of behaviors (sync (default), async, at boot (FPGA)) for each clock domain, but currently only synchronous is implemented. Any issues of guaranteeing proper timing of the async reset signals would be outside of the scope of the auto-generated RTL, so you would have to take care of that manually.

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This looks really cool, I can't wait until I get some time to dig into this and check it out some more. :)

Jack

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