OV7670 vhdl code.

[ahmt_cetin 0]

Hi. I am trying to use Mrs. Hamsters ov7670 vhdl code. But I couldnt make it work. Only frame buffer code is missing and I built a blockram instead from quartus2 but it doesnt working. Is there anybody can help me? 

[offroad 14]

So you're trying to port this to an Altera FPGA?

Of course, the easier way would be to make it work first on the original hardware. Then port it.

If I had to debug this design, what I would do first check for valid HSYNC and VSYNC. Does the monitor recognize the frame timing?
With valid sync signals applied, connecting any color signal e.g. VGA_greeen to 3.3 V should result in a bright (e.g. green) screen. When this works, we know the basic clocks are correct. DISCLAIMER: My monitor does not turn into a fireball when I do this but I don't know about yours.

But as said, porting a design without reference on working hardware is an uphill battle. Besides simulating, maybe it's a good time to buy a Papilio Pro as a logic analyzer which might be part of the 2nd step I'd do.

[Jack Gassett 0]

Excellent advice,

I got Hamsters OV7670 code working on the Papilio but I did have to rely on the SUMP logic analyzer core to get everything working correctly... It is your best friend with getting something like this working. Otherwise you are flying blind. 

Jack.

[alvieboy 24]

I have an implementation for it. let me know if I should publish it (I think it's on an non-published ZPUino branch)

 

Alvie