GadgetFreak

Duo Logic Sniffer External Clock?

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Hi,

I have been testing out the Duo with the Logic Analyzer loaded from the DesignLab.

When configuring there is a dropbox for Sampling Clock but it will not let me select anything other than internal. I need to use an external clock....

Is this not possible with the Duo or do I need to load a different bit file.

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Hello GadgetFreak,

That was a feature that we put into the OpenBench LogicSniffer but I never put into the DesignLab version.

It's pretty easy to expose that external clock pin though, attached is a modified version of the LA design for the DUO that has the external clock exposed:

ext_clock.png

 

It synthesizes correctly but I have not tested it, please let us know if it works. Just connect your external clock to pin 21 on the Papilio DUO board. You may need to edit the config files in the Sump Logic Analyzer to enable that feature...

Jack.

 

Benchy_Sump_LogicAnalyzer_Standalone_External_Clock-160831a.zip

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Took me a while to find the syntax for the cfg file, "INTERNAL, EXTERNAL_RISING, EXTERNAL_FALLING" ;)

It seems to be working but I am not 100% sure as I don't seem to be getting the correct data displayed. In that I set a Simple Trigger Mask of 0x4000 and a Value of 0x0000 as channel 14 is connected to a rom enable line which is active low. It does seem to trigger at the correct time in that it will wait longer if I start the capture several seconds before I know the rom is being accessed. But the displayed data always seems to show channel 14 as high for the whole dump, even at the 0.0us line.

Is it something I am missing about the triggers?

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I have played a bit more and it seems that the capture window size still changes depending on the underlying Internal Clock. I proved this by changing back to internal clock and reducing the frequency then switching back to an External clock and noting the Capture Window time. I am taking the clock from an 8Mhz 68000 CPU and once I slowed down the capture rate to 10Mhz I noted that I do get some variation in the rom enable line but it still does not seem to be working with the triggers correctly or I am getting incorrect data displayed.

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Maybe what you want is an external trigger rather then an external clock? With the external clock I would expect that you need to set the clock in the LA client to match what the actual clock speed is to get meaningful results...

I never did use the external clock feature personally, it was something that was requested when we were making a wishlist of features for the OLS.

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Am pretty certain I do need an external clock as I am looking at chip select and address lines on a PCB using a 68000 CPU at 8Mhz. The only way to cleanly see the line states is to match the clock speed as this is when the transitions occur and by clocking at the CPU speed I can get more capture time. Running at 10Mhz reduces my capture time. There is an issue somewhere with the external clock mode though in that the capture time should be a factor of the external clock whereas in the current code it changes with the 'unused' capture frequency that was selected when the Internal mode was last selected.

The other thing I have noticed is that the RLE mode appears to be bugged. Firstly, I get lots of noise on unused channels in a group, even when I ground them out. And secondly I seem to get square waves whenever a signal goes high and stays high. I have checked this with a scope to verify the line is just high and not pulsing!

So far I am not having much success.... I keep hoping I will find something that I am doing wrong.... but so far no such luck.

There is a switch on the Duo just at the end of the board near the C/D wing connectors. What does it do? Also I presume when using a single LA wing it goes away from the Duo, hanging off the board so to speak?

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If you set your speed to at least double the frequency, so 16Mhz, you should get a clean capture, but like you said that cuts down on your capture depth... You can usually setup triggers to start capturing when the thing you are looking for happen. There are some tutorials for the OLS that show how to setup a trigger to go off when a certain value is on the bus if I'm not mistaken... It might be worth starting out with an internal clock of 20Mhz, only enable the channel groups you need (which allocates more memory to your captures), enable automatic recording size, and then try to setup a trigger when you reach a certain address. That will give you a baseline of what is working and you can see how much data you can capture that way. Worst case scenario maybe you do multiple captures at different addresses.

How many channels are you capturing? Is it less then 8? If so then it might be helpful if I could find some time to get the Logic Analyzer working with the external SRAM on the Papilio DUO board. Since it is an 8 bit part it will be easy to set that up with 8 channels. More channels would take more work...

The RLE uses an extra parity bit that is available with BRAM, or if physical memory is used then it uses the top bit. It is possible that something is misconfigured in the VHDL code and the correct bit is not being used...

Finally, the switch on the board depends on the VHDL code that is loaded. In most cases, and in the case for the Logic Analzyer circuit it is connected to the reset line of the AVR chip. So putting it down will turn the AVR chip off and up lets the AVR run.

Jack.

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Thanks for the replies :)

I am trying to pin down what is going wrong with an emulated chip compared to the original one. The chip basically switches the 2 upper address lines of an eprom under special circumstances. In a dedicated test board it works fine but in the real board it is failing. Originally I was monitoring all 14 address lines and the Output Enable. I was setting triggers to occur on certain memory locations and it seemed to trigger correctly but the data displayed did not match the trigger conditions. So I then tried to simplify it by just monitoring the 2 upper address lines and the Enable. The trouble is without all the address lines I need to capture a much longer data stream, around 500ms, so that I have enough data to compare the whole boot sequence.

I have been coding since the early 80's, both low level & high level, on embedded micros upto minis, but this is my first time playing with an LA. Scopes and logic are no issue normally for me but so far with this board and software I am not getting what I expected to see. Perhaps I should set it all up again with the full set of address lines and take some screen grabs to show you what I am seeing...

Of course a secondary reason for purchase is to start VHDL coding, its that 'little' something that has been missing from my life ;)

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Please do post some screen grabs, maybe it will shake something loose. I've used the LA on the OLS and the Papilio boards for lots and lots of debugging, everything from SDRAM and Camera Interfaces to simple serial data and it has always worked really well for me... It does take some work to get around the memory limitations but the upside is that you can debug things that the other cheap LA's can't touch speedwise...

Jack.

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Hello again,

I now have another LA, its only 8 channels and is an addon for my Scope board.

I have probed the same connections with both, although on the Duo the channels are reversed as I used the same probe cables so as to rule these out of the issue. As you can see from the following 2 pictures the Duo LA seems to generate square waves even when the signal remains high, why is this?

 

Untitled-2.jpg

Untitled-1.jpg

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Looks like you might have the voltage threshold set at a different point between the two? Or maybe no ground connected?

Sent from my iPhone using Tapatalk

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Good suggestions but the cable connection was just moved from one board to the other so all 8 channels were connected and so was the ground and of course all using the same wires to rule a broken wire out.

Not sure about the voltage threshold. Is there an option for this on the DUO?

I am wondering if I have a bad LA wing ?

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It looks like you captured at 10Mhz on the DUO and 16Mhz on the other board. If the signal you are capturing is 8Mhz then you need to capture at least twice the speed according to the Nyquist Sampling Theorem otherwise all kinds of weird things happen... What you are seeing can be the result of not capturing fast enough.

If you capture at a higher speed do you still see this issue?

BTW, I remembered over the weekend that Alvie and I were working on a Wishbone version of the Logic Analyzer. We were 95% done with it but never finished it because it was only able to work up to speeds of 30-40Mhz. This sounds like it would be perfect for your situation though because you just need a capture speed of 16Mhz and the benefit of the Wishbone version is that it would give you access to all of the SRAM on the DUO board on as many channels as you need since the ZPUino SRAM controller takes care of all the memory stuff for us. I'll see if I can free up some time to get that up and running for you this week.

Jack. 

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Ok, if you are feeling brave here is a copy of the library that Alvie and I were working on to use memory over the Wishbone bus with the Logic Analyzer.

This project is setup with 256KB of memory as opposed to the 64KB of memory that would otherwise be available.

This has not been tested very much and I know there is a bug in how memory is handled when the buffer restarts, but it has been so long that I don't really remember enough of the details to fix it without really digging in again to understand the problem...

So here it is as is, it would be interesting to see if this gets you any closer to the capture you need.

To use:

  • Unzip the attached zip file into your DesignLab libraries folder.
  • Open DesignLab and find the new Wishbone_Sump_LA/OLS_Client example.
  • Chose your Papilio DUO board and then load the circuit to your DUO.
  • Upload the sketch to the newly uploaded circuit.
  • Copy the attached cfg file into your Designlab/tools/ols-0.9.7/plugins directory
  • Open the OLS client and select the new DUO Wishbone device type. 

Let me know if this helps,

Jack.

Wishbone_Sump_LA-for-forum_v1.0.zip

ols.profile-papilio-duo-wishbone.cfg

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just given that WB version a quick try but it fails on finding the device, so went back to the standard duo bit file and sampled at 20Mhz. It didn't look any better, so removed the clip probes and went with the jumper wires and the results look better but I still seem to get issues where some lines give a square wave when they are permanently high.

I need to make some time to play and test properly, at the moment I have too many projects on the go and no time for anything really. Also once my spare wing arrives from the USA I can see if that fixes the problem. Thanks for all your help so far and I will keep you posted on my progress.

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Jack,

I too can't get this Wishbone logic analyzer to work for me.  I am using libraries/Wishbone_Sump_LA/examples/OLS_Client.ino (after moving it to a new project).  I had to make some modifications to it since the one in the .zip file does not compile without errors.  It looks like you were changing how buffer was defined and actually have the diff markers in the file.  I just changed buffer to be a defined as a 300000 entry 32-bit array.

When I run the original Logic Analyzer that came with DesignLab, it can find the device on ttyUSB1, and it quickly fills up the buffer when I start the capture.  However, when I download the the Wishbone one and select Papilio Duo-Wishbone Memory, and choose sampling  rate of 2 MHz with recording size 128 KB, it just displays "Capture from OpenBench LogicSniffer started at ...".  If I unplug the Duo board and plug it in again, it displays "Capture failed! Device not found!".

Do you have any ideas why I am encountering these difficulties and have any suggestions on debugging them?  I do have a 2MB Duo board.

Thanks,

Blake

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Jack,

I am also having trouble getting the logic analyzer that comes with DesignLab to actually capture data.  When I load it and an AVR program that just sends "Hello world" out at 115200 bps, I don't see any transitions on the logic analyzer.  I know the AVR program is running since I can set it in the serial port monitor.  In the logic sniffer I am selecting Papilio DUO -64K Memory.  For acquisition I am choosing Sampling Clock Internal, Sampling Rate 1.000 MHz, Recording Size 64.00 kB.  I cycled through Channel Group 0-3 one at a time each in four acquistions, and I didn't see any transitions on any of the channels.  The capture is finishing, so it doesn't seem to be a communication problem.

Do you have any ideas on what the problem can be?

Thanks,

Blake

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Jack,

When I load the DesignLabs logic analyzer into my Papilio One 250K, it works fine.

When I run the original DesignLabs logic analyzer into my Papilio Duo and connect 3.3 volts to the pin labeled MOSI-11, I still see all 32 logic analyzer pins all low (this is done with the AVR disabled).  I am using DesignLab-1.0.7.

Any suggestions?

Thanks,

Blake

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On 9/25/2016 at 10:22 AM, bnusbick said:

Jack,

I am also having trouble getting the logic analyzer that comes with DesignLab to actually capture data.  When I load it and an AVR program that just sends "Hello world" out at 115200 bps, I don't see any transitions on the logic analyzer.  I know the AVR program is running since I can set it in the serial port monitor.  In the logic sniffer I am selecting Papilio DUO -64K Memory.  For acquisition I am choosing Sampling Clock Internal, Sampling Rate 1.000 MHz, Recording Size 64.00 kB.  I cycled through Channel Group 0-3 one at a time each in four acquistions, and I didn't see any transitions on any of the channels.  The capture is finishing, so it doesn't seem to be a communication problem.

Do you have any ideas on what the problem can be?

Thanks,

Blake

Hmm, a couple of questions:

Are you sending "Hello World" out of the hardware serial port? If you are sending through Serial then that is going over the USB port and there is no way to access it with the Logic Analyzer. 

You also need to either put jumper wires between the Hardware serial port pins,(I think pin 0 and 1) and the LA pins (I think on row C and D). Or you can modify the LA circuit to connect to those pins internally..

Jack.

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2 hours ago, bnusbick said:

Jack,

When I load the DesignLabs logic analyzer into my Papilio One 250K, it works fine.

When I run the original DesignLabs logic analyzer into my Papilio Duo and connect 3.3 volts to the pin labeled MOSI-11, I still see all 32 logic analyzer pins all low (this is done with the AVR disabled).  I am using DesignLab-1.0.7.

Any suggestions?

Thanks,

Blake

When you load the Logic Analyzer circuit to the Papilio DUO it should give you a message about how the Logic Analyzer inputs are connected:

"Channels 0-15 are connected to the D Wing and channels 16-31 are connected to the C Wing"

MOSI 11 is on the A Wing so it should not be connected to the LA inputs. You need to use pins 22-53 on the C and D rows to the right side of the board...

Jack

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Hi Jack,

Thanks, now I can get the original Logic Analyzer to work on the Duo.  Since I can't get the one that you modified to work with the Zpuino to sample, could you point me to the source files that you based your Zpuino changes on, which I hope is the original one that works.  Hopefully, by studying the differences I can see what changes are necessary to make it work with the Zpuino, and why there seems to be an issue.

Thanks,

Blake

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Oh OK. It's been a long time now, but I believe we may have started from this one...

example://Benchy_Sump_LogicAnalyzer/Benchy_Sump_LogicAnalyzer.ino

Or we may have just started from a Vanilla ZPUino template...

Jack.

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