Laurence

Does DesignLab rely on (superseded) ISE?

6 posts in this topic

Hi, I am new to  this forum. I am running a course on logic  design and I  want to include a practical introduction to FPGAs. I am considering Papilio as the platform to use as there will not be time to learn VHDL or Verilog. My students are already used to using schematic design tools such as Proteus. We are using Windows 10. Is Papilio the right solution? I understand that Xilinx have superseded ISE with Vivado (which is more complicated and does not allow schematic entry). How does this affect Papilio and DesignLab? Many thanks.

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Hi,

I think you have already answered your own question: Vivado does not support graphical schematic entry (but neither does Vivado support the older Spartan generation so it's not obsolete).

But, for a "practical" introduction to FPGAs: No one uses graphical schematic entry anymore for FPGAs. It just doesn't work in real-world digital design. The Papilio world is different, it lets people connect existing blocks without becoming RTL experts (but that's not for a conventional course on "digital design", IMHO).

How about teaching people a subset of Verilog? For example, this is all I'd need to keep the students busy for a while (+ 5 lines constraints file to map the IOs)

module thisIsMyDesign(input myClk, input mySwitchA, input mySwitchB, output reg myLED1, output myLED2);
    reg [23:0] myCount;
    assign myLED2 = myCount[23]; // divide by 2^24 = 16.7M gives 2 Hz from 32 MHz myClk

    always @(posedge myClk) begin
        myLED1 <= mySwitchA ^ mySwitchB; // XOR. Note, myLED1 is defined as a register in the first line (others are wires)
        myCount <= myCount + 24'd1;
    end
endmodule // note: not checked for typos.

The Papilio boards are great for FPGA learning (also without graphical schematic entry etc, the difference is solely in the design tools) and you can package something like the above example for reuse in a graphical "Papilio-style" design.

Regarding ISE-vs-Vivado: Knowing both Web editions I wouldn't say Vivado is clearly better. Both are different kinds of horrible :-) At least for the ISE version it is guaranteed that it won't change so you won't have to re-do the course material every year.
Reasons to stick with ISE is that Spartan 6 is hugely popular among enthusiasts (Forum support), also most designs will run on USB bus power without a wallwart plug.
 

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PS: Vivado on Windows 10 requires some obscure hacks during installation, or it'll get stuck on some MS runtime package.

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Hello Laurence,

I think that the Papilio, particularly with DesignLab, is a great fit for a practical introduction to FPGA course. It allows students to build some interesting projects by using the schematic editor without learning VHDL/Verilog first, so it lets them see what the possibilities are. It also has all of the VHDL code right there available for the students to study and experiment with if they want since all of the modules are tied together in the schematic editor but they are all defined in VHDL. It's a simple "push" into the schematic symbol to see the underlying VHDL.

The ISE vs. Vivado situation is interesting, I think Xilinx is not explaining it as well as they could be. When they say that Vivado supersedes ISE they are talking about for all the newer generation of chips that they produce. Vivado only supports the Series 7 and newer chips from Xilinx, it does not work with the Spartan 6 and Spartan 3E chips used in the Papilio. Most of the inexpensive boards that you find out there are going to use Spartan 6 chips because the cost of Series 7 chips is still really high. (If the Artix 7 chips were comparable to the Spartan 6 chips in price I would upgrade the Papilio boards in a heartbeat). So while they say that Vivado supersedes ISE it is impossible for them to eliminate ISE any time soon. The only IDE that supports the Spartan 6 chips is ISE... If Xilinx adds support for the Spartan 6 chips to Vivado, or if the Series 7 chips become affordable then I will add DesignLab support to Vivado, but for now ISE is the only option...

As far as Windows 10 goes, that is what I use on all of my machines and all works well. There is a known bug that affects all 64-bit versions of Windows 8 through 10 but it is a fairly easy fix:

http://gadgetfactory.net/learn/2013/09/12/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/

If you want we can send you a sample Papilio board to test out, just send us an email at support@gadgetfactory.net and reference this thread.

Jack.

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Thank you offroad and Jack for your help. I have a much clearer understanding now.

My conclusion is:

ISE is still usable, but not compatible with the newest devices.

Vivado is not a real option as it does not easily run on Windows 10 (and does not offer schematic input).

Papilio with Designlab is a good option for introducing FPGAs.

For teaching FPGA programming, Verilog or VHDL is a must as this is how FPGAs are developed in industry.

It looks like Papilio and Designlab are the way to go for my current students. The syllabus is quite old, so will need to include logic design using old-school logic devices, e.g. 74HC series. As soon as possible I will move them onto programmable logic with them implementing simple designs on FPGAs, initially using schematics. They can analyse the code produced from simple logic circuits, but there would be no need for them to learn VHDL or Verilog at this stage.

Jack - I may contact you outside of the forum regarding your offer.

Laurence

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Sounds good Laurence,

Please send an email to support@gadgetfactory.net with any offline questions you have and it will get to me.

Thanks!

Jack.

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