Coolzire

LogicStart Shield & restart

9 posts in this topic

Hi,

I have been using y papilio duo for a while. My latest project had a issue and i needed to restart the FPGA. With the shield on top it is kinda difficult to reach the restart button. Is there a way to map one of the button to restart the FPGA?

Thank in advance for your time ,

 

-Olivier

Share this post


Link to post
Share on other sites

Hello Coolzire,

It is possible to map a button on the shield to restart your circuit running inside the FPGA, which is the recommended approach. If you tell us more about the circuit you are using I can help to describe how to connect the reset.

Jack.

Share this post


Link to post
Share on other sites

Hi Jack,

I was doing a debouncing circuit with a counter making sure of a minimal pulse width. However I had an invalid state and my circuit would stop responding. I ended up unplugging/plugging the board to reset it while I was trying to debug the circuit. I just looking for a way to use a button from the shield to reset the FPGA as if i had pressed on the reset button on the board, if there is one.

-Olivier

Share this post


Link to post
Share on other sites

Ok, perfect, it is possible to do what you want using the GSR pin on the startup_spartan6 primitive. Here is an example where I have connected Switch0 on the LogicStart Shield to act as a reset:

DesignLab Reset.png

When Switch0 is up the circuit will run, when it is down it resets the same as the FPGA reset pin.

(I determined that Arduino_0 is Switch0 by looking at the following pinout chart: http://www.papilio.cc/uploads/Papilio/Papilio DUO pinout for LS.pdf. You can also use a button instead of a switch.)

I have also attached an example DesignLab design for you to look at.

Jack.

Reset_Example2-160811a.zip

Share this post


Link to post
Share on other sites

Thank for quick replies. It is exactly what I was looking for. I did manage to debounce my input with a synchronizer and a slow clock (400Hz).

I'll implement the reset in my circuit and test it later today.

-Olivier

Share this post


Link to post
Share on other sites

I checked your schematic and like the idea of using the AVR to generate a clock signal for the FPGA. As for the primitive , I am still trying to get it working. I managed to instantiate it in VHDL but my design was not functionning anymore. I am reading the datasheet to sort it out.

-Olivier

Share this post


Link to post
Share on other sites

I got it working with the startup primitive. On my project pressing DIR_UP cause all flip-flop to return to their initial state. I included my VHDL code for the benefits of others.

I instantiate my module with :

HardReset : entity work.GlobalReset port map(DIR_UP);

DIR_UP being the input used to trigger reset.

-Olivier

GlobalReset.vhd

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now