Jack Gassett

Wishbone version of the Sump Blaze Logic Analyzer

24 posts in this topic

So Alvie and I have been talking and we want to work on a Wishbone version of the Sump Blaze Logic Analyzer core. The main benefits of this are:

  • The ability to use SRAM, SDRAM, or DDR ram through the Wishbone bus via DMA transfers. This will get us much more memory available for the Logic Analyzer.
  • It will be much easier to output the captured samples in different formats since it will be C code instead of VHDL code. It will be easy to add support for your favorite Logic Analyzer clients. Not only Jawi's OLS client but special modes for the Saleae client can be easily added as well.

So to get the ball rolling on this effort I've made a special version of the Sump Logic Analyzer core that has its control interface mapped to Wishbone bus registers. This version still uses internal BRAM but I've setup a simulation test bench to make the transition to DMA transfers for RAM easier to work out. The branch on github can be found here:

https://github.com/GadgetFactory/DesignLab_Examples/tree/Wishbone_Logic_Analyzer

 

The commit is:

https://github.com/GadgetFactory/DesignLab_Examples/commit/6019352579070f378304e9f710604b92e0f961cc

 

Or if you prefer a ready to go zip file:

Wishbone_Sump_LA.zip

 

Just open the Chip_Designer.xise file, change to simulation mode, and simulate the Simulate_Your_Chip_Design module as the top level.

 

The next step, moving to DMA memory, is something that's beyond my skills. :) Going to have to defer to Alvie's expertise for the next step, but am hoping to learn from the example of how DMA memory can be used with his new burst controller.

 

Jack.

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Here is a quick video of the simulation in action, let me do a quick written walkthrough:

 

  • How to open and access the simulation.
  • A look at the test bench where the wishbone commands to setup triggers, capture speed, etc are sent over the wishbone bus.
  • How to start the simulation.
  • A look at the decoder to see that it is capturing the correct setup commands from the wishbone bus.
  • A longer simulation time is added, it takes 80 micro seconds to see the entire write and read process.
  • A look at the point where the entire sampling is completed and the write signal goes to a read signal.
  • When this happens data is no longer captured and is instead sent out the serial port. 
  • The address counter reverses and counts down instead of up, we should see that the data that was captured at the last write clock is now being sent out when read is asserted.

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Hey everyone,

 

Alvie and I just had an awesome breakthrough today on getting the Wishbone version of the Sump Logic Analyzer working so I recorded a video to show what we have working:

 

We still have more testing to do, bugs to fix, and things to figure out but this is a huge step in the direction of having a LOT more memory available for the Sump Logic Analyzer.

 

Jack.

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Hi Alvie and Jack,

 

this looks very interesting!

 

Jack, I believe you mentioned before that this project would contain a DMA module. Is this already implemented? If so, could you point out where it is so I can take a look at it?

 

Thanks

Stephan

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Hi Jack, Hi Alvie

 

This looks VERY interesting and could have saved me some work! Sounds like it could be exactly what I was looking for.

 

How would the data transfer to the computer be done? Serial line (USB)? Would this occupy the serial bus? Or could it run in parallel to serial debug output? (Does it use the "JTAG channel"?)

 

(Will this enhanced memory through DMA thingy also become available to other Logic Analyzer implementations as well? Or will this Wishbone Logic Analyzer be the recommended variant for future use?)

 

How can I upgrade by DesigLab setup in order to be able to use such a new library/code? Just clone it to the "libraries" folder? Anything else needed?

 

Sorry for asking that many questions at once. May be some are asked to early.

 

Thanks for this new library! Greetings.

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Jack and Alvie,

I would really like to try experiment with your Logic Analyzer implementation that uses DMA on a 2MB Duo.  In an earlier message you said you didn't have DMA working but could simulate it, and in a later message you seemed to suggest that DMA is working.  If I want to use your latest  version, where should I get it, and what works and what doesn't?  In your video, it is not using the OLS client, but instead is using an Zpuino program and the terminal.  Is this still the way it works?

Thanks,

Blake

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Well, I just tried to see if it works on the Papilio Pro and I didn't get a response using the OLS client. I only have about 15 minutes to put into it this morning unfortunately. Here is the latest version, you can unzip it into the libraries folder of your DesignLab installation and then find the Winsbone_Sump_LA/OLS_CLient example under Examples in DesignLab. You will then need to load the circuit to your board, load the sketch, and open the OLS client and try to connect to it. 

The status that we left off was that it was 80% working and just needed some bugs in the OLS_CLient sketch to be worked out...

Development fell off because we discovered that the performance is not that great. The best that we were seeing was about 30Ms/s...

Jack.

Wishbone_Sump_LA.zip

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Hi Jack,

When I tried to generate a programming file after setting wb_core as top module (which I think is what you suggested in the Back to Basics thread), it gets the following error when running the map:

IO Utilization:
  Number of bonded IOBs:                       192 out of     102  188% (OVERMAPPED)

Is there something additional I need to do?

Blake

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Hi Jack,

When I tried to generate a programming file after setting wb_core as top module (which I think is what you suggested in the Back to Basics thread), it gets the following error when running the map:

IO Utilization:

  Number of bonded IOBs:                       192 out of     102  188% (OVERMAPPED)

Is there something additional I need to do?

Blake

Hey Blake, you shouldn’t change the wb core to the top level. Leave the file that is the top level when you open the project as the top level. Then select that and hit generate programming file.

Sent from my iPhone using Tapatalk

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Jack,

Thanks for the quick reply.  Before reading your reply, I changed the top level to BENCHY_sa_SumpBlaze_LogicAnalyzer32 and it successfully created the programming file.

Blake

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Hi Jack,

It depends what you mean by getting it to work.  I won't list all the tool issues I have that cause ISE to hang when launched from DesignLab, because I seem to have found ways to get around them.

Where I stand now:

1) When I regenerate the bit file, it seems to be binary equivalent to the one that in the .zip file, which is encouraging.

2) The capture completes when I use the bit file and choose WB anything less than 256KB memory in the logic analyzer menu.  However, when a feed a known frequency such as 100 KHz in, it thinks it is 66 KHz (at least in one attempt).  When I load the regular logic analyzer bit file and choose Duo 64K, it correctly sees the frequency as 100 KHz.  I am now going to look into the discrepancy.  My plan is to add two GPIOs to the arduino sketch and toggle out all the values receive from the serial port, send to the serial port, and read from the wishbone bus out the two GPIOs in SPI fashion.  Once I understand how the logic analyzer protocol works, I will start digging into the VHDL code. I will use my Papilio One in logic analyzer mode to view the GPIO toggles.

Blake

 

 

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There are some changes that need to be made to the configuration file for the Sump logic analyzer client to accept larger sizes from what I remember...

Also, around 30Mhz was the fastest speed I remember this working at and there were some problems at the start and end of the capture that I didn't get working. If you send a series of ASCII characters over the serial port and capture them you will see the problem.

Jack

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Jack,

When I configure Zpuino GPIOs 14 and 15 as output and try to toggle them, I see no output in OLS_Client.ino.  (When I modified the timer example to do the same thing, I did see the GPIOs toggle.)  When I looked at the ucf file for the logic analyzer, it just had the 32 logic analyzer inputs and tx and rx.  if I want to have additional GPIOs for use by Zpuino, do I need to modify the VHDL code for the wishbone logic analyzer?  I am guessing the vanilla Zpuino defines all the GPIOs for use by Zpuino, but the Zpuino used by the logic analyzer takes some of this capability away.

Blake

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Never mind.  Looking at the schematic, I see that only Arduino 0-13 are assigned.  When I switch to using 12 and 13, I see the toggles.

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Jack,
 

When I use the attached test program, if I modify SendIfReady() so it sends a test pattern, the capture completes successfully if I mask out bit 4, but if I don't mask bit 4 out, the capture doesn't complete until I upload new code, at which point it completes and displays the bit 4 value correctly.  It is as if it is hanging draw channel-4.

I don't see how the value of the data should affect whether the capture completes.  I am pretty sure 1024 bytes is the correct amount to send, since if I send less than that with bit 4 masked, the capture won't complete until I upload new code.

What would be required to debug the Java LogicSniffer Client program to see if it is in fact receiving all the data?

Is there a way I can monitor the serial line to see if it is actually sending all the data?

To get it to hang, just modify the following line:

    Serial.write(test_val++ & 0xef);

to:

    Serial.write(test_val++ & 0xff);

I have configured the Logic Sniffer as follows:

Connection: Papilio DUO - Wishbone Memory

Acquisition: Sampling Rate 5.000 kHz, Channel Groups 0, Recording size 1.00 kB

Blake

 

 

 

OLS_Client.ino

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Hello Blake,

I'm pretty sure you can use Eclipse IDE to debug Jawi's OLS client. Jawi has some instructions for how to use Eclipse on his github page:

https://github.com/jawi/ols

Thats what I was using and I remember it was pretty helpful. You can also use a serial port application that is capable of sending binary data such as hercules or realterm.

Here are my notes from debugging with the serial port:

Usefull posting that shows a breakdown of what command to send for debugging in hercules:
http://dangerousprototypes.com/forum/index.php?topic=549.0


To reset	00 00 00 00 00 02
To Init	C0 00 00 00 00 C1 00 00 00 00 C2 00 00 00 08 80 00 00 00 00 81 ff 01 ff 01 82 02 00 00 00 
To start capture	01

The time for 9 cycles as measured above should be (1/115200)*9 = 78us


Bad	good	character
78	80	0b00110001
78	80	0b01000001
76	80	0b01001100
78	75	0b01010011

Jack.

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Hi Jack,

I was able to debug the OLS application in Eclipse.  When it was hanging, the host was receiving all 1024 characters, but was hanging when the host was in the loop sending CMD_RST five times.  It was actually hanging the second time it sent the CMD_RST.  When I modified the source so it would only send  CMD_RST once, it hung on closing the port (it does this after every data acquisition).

Since this seemed to be a driver issue below OLS, I went back to trying to figure out why it hangs when I send a certain sequence.  I was able to isolate it the value 0x13, which is the flow control character.  If I take the Papilio 250 with the standard OLS client and short channels 0, 1, and 4 to 3.3 volts, it hangs the exact same way (I am only using Channel group 0).  I would think the solution would be to get both sides to ignore flow control. Do you have any thoughts on how to achieve this?

I am running on Linux, so I don't know if it would display the same behavior on Windows.

Blake

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Jack,

When I replace the following in LogicSnifferConfigDialog.java:

      result = String.format( "comm:%s;baudrate=%d;bitsperchar=8;parity=none;stopbits=1;flowcontrol=xon_xoff",

with:

      result = String.format( "comm:%s;baudrate=%d;bitsperchar=8;parity=none;stopbits=1;flowcontrol=off",

it no longer hangs when I send the test pattern, or when I make channels 0,1, and 4 high on the Papilio One 250K OLS client.

Having a logic analyzer hang when it receives 0x13 during data acquistion is very undesirable to me.

Blake

 

 

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Hey Blake,

Are you talking about Jawi's OLS client or the original sump client?

I don't recall ever seeing the problem you are talking about... 

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