terryphi

Error When Driving Counter and DCM Simultaneously

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Hi There,

 

I know 'can you please debug code' posts are generally frowned upon, but I'm having a bit of trouble with what, I think, should be a trivial problem.

 

What I'm trying to do is connect the 32 Mhz clock pin to a counter as well as a DCM, but when I do this, I get the error

"Port <CLK> has illegal connections. This port is connected to an input buffer and other components."

 

When I hook the counter or DCM up separate, there is no issue.  Can I only have the clock signal going to one location?  Is there some sort of signal divider?

 

My main VHDL file is as follows:

ibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity main is    Port ( LED : out  STD_LOGIC_VECTOR (7 downto 0);           SWITCH : in  STD_LOGIC_VECTOR (7 downto 0);           CLK : in  STD_LOGIC);			  end main;architecture Behavioral of main issignal counter : STD_LOGIC_VECTOR(29 downto 0);COMPONENT cnt	PORT(		clock : IN std_logic;          		total : OUT std_logic_vector(29 downto 0)	);END COMPONENT;	COMPONENT dcm2	PORT(		CLKIN_IN : IN std_logic;          		CLKFX_OUT : OUT std_logic;		CLKIN_IBUFG_OUT : OUT std_logic;		CLK0_OUT : OUT std_logic		);	END COMPONENT;begin	Inst_dcm2: dcm2 PORT MAP(		CLKIN_IN => CLK,		CLKFX_OUT => open,		CLKIN_IBUFG_OUT => open,		CLK0_OUT => open	);	Inst_cnt: cnt PORT MAP(		clock => CLK,		total => counter	);LED <= COUNTER(29 downto 22);end Behavioral;

The counter code is:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity cnt is    Port ( clock : in  STD_LOGIC;           total : out  STD_LOGIC_VECTOR (29 downto 0));end cnt;architecture Behavioral of cnt issignal counter : STD_LOGIC_VECTOR(29 downto 0);beginclkProc : process(clock)begin	if rising_edge(clock) then		counter <= counter+5;	end if;	total <= counter;end process;end Behavioral;

and the DCM setup is:

pfwrDxj.png

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Hello terryphi,

 

These types of questions are not frowned upon at all, please ask away - we are here to help. :)

 

Ok, so when you connect the clock to a dcm the Xilinx tools will automatically instantiate a global in clock buffer. That will cause the clock to be routed to the DCM through the global clocking fabric. When that happens it will complain if you try to connect anything else to it. The solution is easy once you know it though, connect your clock to just the DCM and then use CLK0 from the DCM to feed a clock to the other items in your design. CLK0 is the original 32Mhz clock passed through the DCM.

 

You will want to create a signal for CLK0 and connect the output from the DCM CLK0 to it, then connect the signal to your counter.

 

So its usually a good idea to run your clock straight into a DCM and then use that DCM to generate whatever clocks you need.

 

Please ask away if you run into anything else.

 

Jack.

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Hello terryphi,

 

These types of questions are not frowned upon at all, please ask away - we are here to help. :)

 

Ok, so when you connect the clock to a dcm the Xilinx tools will automatically instantiate a global in clock buffer. That will cause the clock to be routed to the DCM through the global clocking fabric. When that happens it will complain if you try to connect anything else to it. The solution is easy once you know it though, connect your clock to just the DCM and then use CLK0 from the DCM to feed a clock to the other items in your design. CLK0 is the original 32Mhz clock passed through the DCM.

 

You will want to create a signal for CLK0 and connect the output from the DCM CLK0 to it, then connect the signal to your counter.

 

So its usually a good idea to run your clock straight into a DCM and then use that DCM to generate whatever clocks you need.

 

Please ask away if you run into anything else.

 

Jack.

 

Great, thank you!

 

Given that, my other question I have is: how would I find this out without using the forums?  Is there some sort of "clocked resources design guide" or something where I can read more about this?

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Hello,

 

You need to better understand how the clocking infrastructure works in the Spartan 6 FPGA. Here is the relevant document:

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

 

You will be most interested in:

  • Global Clocking
  • Global Clock buffers
  • Input and Output Global Clock buffers

 

I don't know if the guide tells you this, but there is a setting in ISE that will automatically put global clock buffers on clock inputs and outputs. It's important to know that happens too.

 

Jack.

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Hello,

 

You need to better understand how the clocking infrastructure works in the Spartan 6 FPGA. Here is the relevant document:

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

 

You will be most interested in:

  • Global Clocking
  • Global Clock buffers
  • Input and Output Global Clock buffers

 

I don't know if the guide tells you this, but there is a setting in ISE that will automatically put global clock buffers on clock inputs and outputs. It's important to know that happens too.

 

Jack.

Sorry, I'm using the papillio one board, so it would be the Spartan 3 guide wouldn't it?

 

Is this the relevant guide?

 

http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

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Ah, yes, that is the right one for the Spartan 3E. With the Spartan 6 they split things out to different guides, the Spartan 3E was all in one pdf.

 

Jack.

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Hi,

 

the problem seems familiar.

If the built-in clock generation block allows multiple clocks, you can simply set an unused output to 1/1 ratio.

 

I think I once solved the problem for myself by editing the generated (PLL) component, ripping out the IBUFG and putting it into the toplevel design. Its output is accessible. But I may remember this wrong.

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