Speeder

Papilio one check if it is okay

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Hi,

 

I have a papilio one and am using it for getting data from an OV7670. However after several attempts , I observe that the VSYNC from the camera comes into the papilio correctly , but this same VSYNC(without any modification) if latched and sent to another pin seems to have many glitches. This is surprising since the simulation shows no problem and the VSYNC is coming corrctly. It is also a low frequency signal . Is there any way I can check to see if the Papilio is okay, and if there are some problems on the board itself? COuld you upload the bitfile I give you and check if you are seeing the same problem?  Please let me know how to proceed.

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Hello Speeder,

 

How are you determining that VSYNC has glitches? Maybe one of the best things you can do is use the Sump logic analyzer included in DesignLab to capture all of the video signals to see what is happening. 

 

Jack.

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That is probably not fast enough to measure VSYNC, you need to capture at least twice the speed to get an accurate waveform.

 

The Sump Logic Analzyer in DesignLab can be embedded into your design and can go up to 200Mhz.

 

Jack.

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Speeder I know this doesn't address your last question but one way I have used to look at fast pulses that happen infrequently (like I believe your sync pulse is) is to create a test signal that toggles one time for each pulse. That will need a slower sample rate than is required for a fast pulse on your logic analyzer and may work the way your setup right now. This test signal lets you know that at least something is being generated at the appropriate interval. If you have an oscope you can check a single pulses integrity in a separate test, or maybe use your logic analyzer in a lower channel mode (1 or 3 channels or whatever your lowest setting is) so you can increase your sample rate. Like Jack said, you need a sample rate of at least two times your fastest pulse to see the signal otherwise you will alias.

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Speeder,

 

There is a tutorial here:

 

http://gadgetfactory.net/learn/2015/07/30/designlab-using-papilio-as-stand-alone-logic-analyzer/

 

If you look at the table of contents in DesignLab you will see a project showing how to embed the logic analyzer in your own projects. You can easily convert your existing project to a schematic project and then attach the Logic Analyzer to it schematically. You can also pull the VHDL code out of DesignLab but that is beyond the scope of what we are doing with DesignLab, but still possible and shouldn't be very hard.

 

Jack.

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Actually, I just remembered that I was working on a project to capture video from the OV7670 and push it out to the VGA adapter a couple of months ago. I never got it to work properly but it is an example of how you can setup an OV7670 project with a Logic Analyzer. I found that the Logic Analyzer was invaluable in debugging what was going on...

 

Camera7670_to_VGA_notworking.zip

 

Jack.

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@treadstone, yes, That is definitely one way to do it. I did try that though. However I am still unsure as to whether glitches can be caused by the problem you mentioned. 

 

@jack, could you upload the remaining files you have used as a reference in the project. There seems to be alot of files which are not found. Also , I am more interesed in using this like chipscope where I would like to call it in VHDL. Is there some files that need to be added? I already have a project. I dont want to bring out the pins on the papilio as logic analyzer pins. Instead I want to internally connect them to view it. Could you please help me out?

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Speeder,

 

All the files are there, you need to open it up with DesignLab. You can't just open it directly with Xilinx ISE...

 

The included design does not bring out the pins on the Papilio as Logic Analyzer pins, it is actually setup to use a OV7670 Camera Wing connected to, I think, Wing Slot C. The Logic Analyzer symbol then connects to those pins internally so you can see what is going on.

 

Jack.

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Hi,

 

Thanks for the reply. I opened it up with design lab and looked at the ZPUINO file. There doesnt seem to be any logic analyzer module connected to it.  I opened the Camera7670.ino using design lab and clicked edit circuit.

Now in Xilinx, where should i look for the analyzer module? I am not able to find the source for the .ngc blackbox file. Is it located in this?

 

What is the huge 200 pin wing coming into ZPUINO? 

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Ah, sorry, you need to change your board type to Papilio DUO or Papilio Pro, I was doing the work primarily on the Papilio Pro...

 

The 200 pin Wing maps the GPIO to the ZPUino Soft Processor. It's not actually 200 pins, the bus is just that wide for future growth... Its only using 48 pins for the Pro and the One and 54 pins for DUO. The rest get optimized away...

 

Jack.

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