michaelclary

Project: 12MHz Synchronous Serial Communication

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Hello all,

 

I have a project to simulate a communication with a board that uses a protocol which looks like the SPI but is not exactly this.

The clock speed is 12MHz and at each falling edge, I have a bit of the frame on the data line.

A frame is between 10 to 32 bytes starting with one start bit and stopping with a CRC32 and a stop bit.

The clock is generated by the master and I need to develop the Slave of this protocol (I d'on't need to generate the clock during the answer).

At this moment I know the entire frame I need to answer to and I know also the answer (these never change) but for future use, I will need to check the CRC32 and generate a frame according to the request of the master (full protocol).

I'm sure that this can be done with a Papilio board but I need a confirmation of this.

Wich board do you recommand for this (Papilio Pro?)?

 

Thanks for your time.

 

Michael

 

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Hi Michael,

 

it may be a good idea to pick an extra board that can double as logic analyzer. It's not exactly necessary but it can be extremely valuable to watch both signals and internal states of the circuit routed out to GPIOs.

An experienced designer won't need it. That said, just as Jack wrote any cheap FPGA will be sufficient for both source and sink at the same time.

 

There are two design philosophies for this sort of circuit:

  • The easy one is, run the detector at an arbitrary (high) clock to sample the signals, including the clock. I have used this approach with a ~160 Mhz clock on a 26 MHz SPI-ish signal buzzing round in a cell phone.
  • The not-so-easy and possibly faster one, which is more ASIC-style, is to use the clock signal as a "true" edge-triggered clock.

Most likely, you'll be better off with the former, at least up to 50 MHz or so. I'm just pointing this out, because many ASIC-driven textbooks will steer you towards the latter.

Otherwise, the job is a straightforward application of state machines and shift registers.

 

PS Keep in mind to register all incoming off-chip signals, it's the #1 FPGA gotcha in this sort of circuit (otherwise two internal nodes will sooner or later sample at slightly different times and reach a different result. What happens is very hard to debug).

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Thank you very much for your answers.
I prefer the solution with the clock signal as edge-triggered clock for the final solution.
I think, for the first phase, I will uses samples of the signals at an high clock. By using this, I will be able to "see" what is happening on the bus.

 

Thank you.

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Hi,

 

>> the solution with the clock signal as edge-triggered clock

some more hints:

- There will be a clock domain crossing to the main circuit with its own clock. It's a textbook topic, but not a trivial one.

- Think about reset logic in the absence of a steady clock.

- Check, whether you can get the final byte out, when the clock stops. Often there is one extra clock cycle defined in the standard for this purpose.

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