J1b on Duo tryout

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Hi to all

My question May be ot:

I'm trying to understand the j1 cpu. After read the original paper and see j1a and j1b cpu I'll see there are some differences but I can't find any description of this new versions of cpu.

In particular I can't understand the _IORD_ alu function.

Can anyone explain me how exactly works?

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Here's what I think is going on, based on looking at the code in https://github.com/jamesbowman/swapforth/tree/master/j1b/verilog.  I think it indicates a read from some I/O device's registers.  That is, instead of reading/writing memory, the instruction reads some data provided by one of the peripheral devices.

This is one of the common ways a computer design could allow access to I/O devices.  It looks like J1B uses a mixture of port-mapped and memory-mapped I/O (see https://en.wikipedia.org/wiki/Memory-mapped_I/O): as I look in xilinx-top.v I see that some memory accesses go to registers such as "uart_baud" too.

Analysis in more detail:

In j1.v: When "insn[6:4] == 5" then func_ior is asserted to 1.

When that is true (along with some other things) then the output signal "io_rd" is asserted to 1.

In xilinx-top.v: The signal io_rd is delayed one clock cycle (as io_rd_) and used, along with mem_addr (delayed as mem_addr_), to receive from the UART (see the signal uart_rd).


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