Welcome to the J1 Forth CPU Discussion

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Hi All,


Welcome to the J1 discussion area of the Gadget Factory Forum.


The J1 is a compact, open source cpu, with a stack architecture optimised for executing the Forth language.


It is ideally suited to fit into a variety of FPGAs, and James Bowman, the designer, has kindly made a build available that suits the Papilio hardware - specifically the Papilio Duo fitted with computing shield.


Stack processors have been around quite a while - as described ion Philip J. Koopman's 1989 book "Stack Computers: The New Wave"


The book introduces the concept of the stack computer and offers a detailed examination of 7 such examples both 16 bit and 32 bit.


The book reviews stack computers that were being developed in the mid-1980s, at the same time as the ARM RISC architecture was in its infancy.


In 1985, Charles H. Moore introduced the Novix NC4016 - a 16 bit stack computer based on a gate array.  This device was revolutionary in it's day and faster than the nearest Intel x86 offering - despite the fact that it used only 1% of the transistors of the Intel part.  It ran at 8MHz and showed how hardware and software could be optimised together for speed and efficiency.


The J1 is a close descendent of the Novix,  James Bowman has incorporated many of the ideas pioneered in the NC4016 and adapted them for efficient implememtation in FPGA hardware. The result is a 32bit Forth processor in a common Xilinx FPGA that runs at 180MHz.


I would like to invite you to join a journey of discovery into the fascinating world of soft core processors, stack machines and the Forth language.



Ken Boak




London  13th September 2015

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Hi to all

My question May be ot:

I'm trying to understand the j1 cpu. After read the original paper and see j1a and j1b cpu I'll see there are some differences but I can't find any description of this new versions of cpu.

In particular I can't understand the _IORD_ alu function.

Can anyone explain me how exactly works?

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