breakin

AVR to FPGA communication

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note: Solved, the problem might have been related to having the incorrect board selected.

 

Hi,

 

I'm trying to communicate between the AVR (hard core) processor and the fpga.

I've verified that AVR works. I can do serial, blink LED 13 etc, blink LEDs on my breadboard etc.

However I'm having troubles "connecting" one of the AVR-compatible pins to a FPGA-pin.

Would be happy for any help I could get!

I'll be happy to make a tutorial/example once I figure all of this out

Details:

 

I'm opening a pin (using pinMode) on the AVR side as an output.

I'm accessing that same pin in my ISE schematics and just routing it to an output (say Arduino_40).

I've tried different pins (with 0-14 as output from AVR and all the CH-wing pins as outputs).

My schematics has no zpuino, all there is what you can see from ise.png plus the AVR disable/enable bit.

 

In order to route an input directly to an output I had a to make a really simple VHDL-snippet that just routes the value. See breakin_passthrough.vhdl. The problem might be in me misunderstanding how this is supposed to work.

 

Sidenote: I'm avoiding wishbone since it relies on zpuino and I want the SRAM all to myself in the fpga.

 

In my sketch I do

 

void setup() {

   pinMode(13, OUTPUT);
}
 
and in loop I do
 
void loop() {
 digitalWrite(13, HIGH); delay(500);
 digitalWrite(13, LOW);  delay(500);    
}
 
I've chosen 13 so I can see the LED blink when it is running, but I've tried other ones as well.
 
Thanks again!
 
ps. See this thread http://forum.gadgetfactory.net/index.php?/topic/2415-communication-zpuinofpga/for a discussion on what I'm trying to do and why I want to avoid the zpuino for now.

breakin_passthrough.vhd

post-38993-0-92452900-1441624728_thumb.p

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Sidenote: I'm avoiding wishbone since it relies on zpuino and I want the SRAM all to myself in the fpga.

 

Actually... not.

 

You can have a full wishbone bus without ZPUino, just needs some rewiring. Right now there are two/three wishbone bus masters: ZPUino, the DMA channel, and the SPI slave.

 

If you hook the bus to the SPI slave, you can remove ZPUino (and you can use full SRAM).

 

You can also use ZPUino with internal RAM if you wish. Again, requires just a bit of rewiring.

 

Alvie

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Actually... not.

 

You can have a full wishbone bus without ZPUino, just needs some rewiring. Right now there are two/three wishbone bus masters: ZPUino, the DMA channel, and the SPI slave.

 

If you hook the bus to the SPI slave, you can remove ZPUino (and you can use full SRAM).

 

You can also use ZPUino with internal RAM if you wish. Again, requires just a bit of rewiring.

 

Alvie

 

Hi Alvie,

 

First thanks for zpuino, it is really nice for what it wants to do! Nice to know what I can do wishbone without the zpuino! That you can choose to use zpuino without SRAM also changes the discussion in my other thread.

 

That said; I have to understand why my avr<>fpga-communication doesn't work because otherwise I will forever be clueless (it is such a simple concept) but I might eventually use the wishbone instead!

 

With regards to me using zpuino; I decided to get the papilio because it had lots of fast SRAM that was ideal for what I wanted to do (not just this I'm doing now but other ideas as well). Downside was low amount of blockram and ISE instead of vivado (that I've heard a lot of good things about). As such I don't want a soft core that hogs the SRAM. I'd also want most of the block ram for myself. For other application the DMA interface is ideal. I think my ideal solution would be a softcore that had a register shared with the fpga, mostly only did SPI/serial and had SRAM access but only when nobody else needed it. Since that is almost what the AVR is I'm going for that first (if I can get it to work).

 

Thanks again for reading and commenting!

 

Cheers,

Anders.

/Anders

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I might have figured out the problem. It seems I was a bit unlucky when I choose Arduino_40 as my output.

It seem to work for all other pins in the CH-wing now, triggered from most of the 14 AVR-pins.

 

So the question is why? At least on the microSD-wing the pin that goes into Arduino_40 (when placed in wing CH) is the MISO (master input, slave output). It is not supposed to be an output pin. If I hook up all 8 pins two more are not working as outputs from the fpga (namely the Arduino_50/52).

 

That is only 5/8 are working for me as outputs. I tried with CL as well and it behaved the same.

I was assuming that the wings just had 8 bidirectional pins (for a 8-bit wing). Could anyone help set me straight?

 

Thanks for reading!

 

ps. I don't remember having this issue when I had the AVR disabled and ran with power from FPGA instead (all zpuino). I think it worked there...

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Ok problem solved. I must have selected the wrong board prior to my first start of ISE or something because recreating everything from scratch just made everything work.

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