hroyster

Using Papilio Pro Templates in DesignLab 1.0.7

17 posts in this topic

I am relatively new to the Design Lab use.

 

I get the following error when I try to compile the examples in Xilinx ISE.

 

The following error messoge comes up. "ERROR:HDLCompiler:410 - "C:\_Data\Papilio\Projects\Multiple_Serial_Ports\circuit\LX9\Papilio_Pro.vhf" Line 223: Expression has 148 elements ; expected 201"

 

It looks as though there is a mismatch in the bus dimensions. Am I doing something wrong?  I chose papilio pro from the board selector.

 

I tried several of the examples and the bus mismatch still remains.

 

Thanks in advance for any help.

 

 

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Hello hroyster,

 

Are you opening the Xilinx projects directly or through the DesignLab IDE? The DesignLab IDE actually modifies the xise project files to add some library files so it is no longer possible to open the xise file directly, it needs to be done through the DesignLab interface.

 

The other question is, did you ever install any of the earlier Papilio Schematic library stuff where you had to manually enter the path to the Papilio schematic library files? If you did then those old files could still be setup in Xilinx ISE and overridding the newer designlab stuff. I would be sure to remove any Papilio Schematic library stuff and any older versions of DesignLab.

 

Here are some tutorials showing how things should work:

http://gadgetfactory.net/learn/2015/04/03/designlab-using-the-ide-for-the-first-time/

http://gadgetfactory.net/learn/2015/04/03/designlab-hello-world/

http://gadgetfactory.net/learn/2015/05/08/designlab-editing-a-zpuino-system-on-chip-circuit-2/

 

Please let us know how its coming.

 

Jack.

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Thank you Jack for the quick reply.

 

Yes, I have the old zap versions and libraries associated. I will remove them.

 

I did open the files directly with DesignLab and use the edit circuit feature of the arduino style interface to open XISE.

 

I will remove the files and try again.  While waiting I also used the RTL feature of ISE to see what the mismatches were. The old zupino Papilio pro had different bus dimensions.

 

Was this to make room for the Duo?

 

Thanks again,

 

 

Howard

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Yes, the different bus dimensions came about when I was adding the DUO, it has more GPIO pins. I realized that I could avoid having to constantly changing the buses for new boards by simply making the buses much bigger. The optimizer removes the unused elements and we have the benefit of not having to inconvenience people with changing the interface in the future...

 

Jack.

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Jack,

 

I will clean out the old libraries, but I did check each of the VHDL references in the project and they all point to the repositories from DesignLab-1.0.7.

 

Could they still be wrong?

 

Howard

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Well, I think even if the paths in the xise file are correct the files in the library directory will still override them. 

 

Jack.

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Jack,

 

I cleaned out the libraries from the prior installations.

 

Further scrutiny reveals that the problem in my setup is not the VHDL repositories. I was able to directly modify the derived Papilio_Pro.vhf that is built by compiling the .sch file

(which is from the DesignLab-1.0.7 library). I was able to compile the project, download the bit file to the pro board, and run my sketch (it reads files from the SD and plays an animation sequence

on a VGA monitor. It is quite fast even though it is writing every pixel from code.

 

Below are the 3 entries in the Symbol Library Manager under the Tools section of the XISE

 

C:\DesignLab-1.0.7\examples\00.Papilio_Schematic_Library\Libraries\Xilinx_Symbol_Library\Papilio_Schematic_Library.lib

 

C:\DesignLab-1.0.7\libraries\ZPUino_2

 

C:\DesignLab-1.0.7\examples\00.Papilio_Schematic_Library\Libraries\Xilinx_Symbol_Library\Papilio_Schematic_Library.cat

 

I tried from scratch the following:

 

Opened Design Lab 1.0.7

Opened the examples-gfxdemo sketch

Pressed edit to create modifiable new project directory gfxdemotest

XIse opens at the new project directory

Checked the vhdl paths and the schematic paths, all point to Design Lab 1.0.7

Highlight the top gfxdemo1.sch file and press synthesize

Get errors with the bus dimension incorrect.

 

I still have trouble with the .vhf file not being directly compiled correctly.

 

Have I still missed something?

 

This is not such a big deal for me, because I predominantly use top level VHDL files.

 

I would like to be able to use the schematic entry in the future.

 

Thanks again for any help. I would like to find out where my error is coming from?!?

 

Howard

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Aha! That is the problem, you need to completely remove those Symbol Library manager entries. Those entries have not been necessary since the first version of DesignLab, they were only necessary under ZAP and the Papilio Schematic Library. So you should be able to go under the ISE settings and remove all Symbol Library entries. 

 

Some quick history about the change:

  • First of all, I didn't want people to have to manually add those Symbol Library entries. But I didn't see any way around it...
  • However, when I went to port everything to work with the Linux version of ISE I was dismayed to discover that those Symbol Library entries didn't work under Linux anyways!
  • After about a week of trying to get something to work under both Linux and Windows I stumbled across the undocumented feature that ISE will automatically add all files in a directory to its path if you include an *.edif file. 
  • I realized that including an *.edif file would work for both Linux and Windows and would remove the need for people to manually enter the Symbol Library entries. So I dropped the Symbol Library manager and went with that method instead.

Jack.

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Jack,

 

OK Now I know where the incorrect references are coming from.

 

I have tried to remove the symbol libraries, but with no success. The tool will not let you simply remove those references, and even I remove each of the categories and components in the tool, it still generates an incorrect bus config(147 to 200 mismatch). I even tried removing the symbol files altogether, but still no success. It seems that only if you point it at another valid symbol library will it let go of the exisiting ones.

 

I continue (over years) to have configuration difficulties with xilinx tools of this nature. If you have a known sequence to remove this library, I will try it.

 

I have converted the top level module to VHDL(renamed vhf file) and am able to make changes to the core configuration at will. I will continue to try and get the schematic editor to work, but as in the past I have battled xilinx tool errors in the past to no avail, I will not break my pick on this one either, unless you or some one else in your network has a formula for disconnecting the symbol library as you suggest.

 

I would like to comment positively, however, on your efforts to develop an integrated tool for soft cores and embedded code for FPGAs. You and your associates work are nothing less than brilliant!!

 

I believe the future to be embedded processors in FPGA fabric. After all, Intel just acquired Altera - that says it all.

 

And the flexibility of the papilio family is well thought out.

 

Thanks again for the help.

 

Howard

 

Again,

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Jack,

 

Excellent !!! Worked like a charm. I will explore the schematic control of the designs now that I am free to edit and compile.

 

Hoped I helped some others as well. Early adopters would have had the same problem as I had.

 

I wanted to quickly give some background on my interest and current project with the papilio.

 

8 years back I started building a large aperture telescope mount - 1 meter

 

To control it I developed it using the opencores 8080 verilog core. I built up a 50MHz processor running digital research pascall from the 80's.

 

After debugging the processor, I added macs and a national Phy and implemented 100 Mbit ethernet.

 

For an 8080, this thing screamed. I ran it on the digilent spartan 3 board with the 1000 chip in it.

 

I am able to control cameras and digitize and transmit the imagery to a central PC.

 

My plan is to now replace the 8080 with your much more code friendly papilio board when I add the Mac and Phy.(it already with do all the telescope control)

 

The telescope can be seen on my fledgling website eyetothesky.com

 

I mention this because if someone is already working on a mac for the papilio, I do not want to recreate the wheel.

 

Again, my praise to your effot on this platform. It is clearly the brightest link I can find to parctical integration of an idE that FPGA and Arduino experimenters can use.

 

Howard

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Howard, 

 

Thank you and I'm very glad you got the issue sorted out and can get cracking on your telescope project. :)

 

The telescope project sounds really awesome. :)

 

For the mac on the Papilio, we have an RMII PHY design out there, but we never got a mac controller working with it. As far as I know there is no one else working on one either... Let me know if you are interested in the RMII Wing design.

 

Jack.

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Jack,

 

Thank you for the positive feedback. I wil begin to adapt the Mac design to the Papilio in a few weeks. My concern is some of the timing changes moving from the 50Mhz 8080 to the 96Mhz papilio.

 

I will send more feedback later, probably better off in a new thread.

 

A little more update. I re implemented my test project with the schematic editor, and got it running very quickly. It validated when I downloaded the bit file.

 

One question though. I did not know what to connect the the Flex circuit wires in the Papilio_Default_Wing_Pinout. It also looks like there was a mismatch of the component as the library showed the flex circuit was commented out in the vhdl of the Papilio_Default_Wing_Pinout. Is there a way to complete the flex when it is not connected to anything??

 

Thanks again.

 

Howard

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Howard, the flex pins let you move the location of a pin programatically, you can look at the table of contents to find a project that shows how to use the flex pins. If you don't want to move pins using code in your sketch then just leave them unconnected and they will be optimized out.

 

Jack.

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Jack,

 

I have move forward in my design and added arotary encoder to make a variable input to the papilio. I started by using the encoder wing example from the Robot_Control_Library. All went well but when I synthesized it, and error pop up that the flex connections in the Papilio_Default_Wing_Pinout component did not match the library.

 

It reads "ERROR:HDLCompiler:1156 - "C:\_Data\Papilio\Projects\Encoder_Wing3\circuit\LX9\Papilio_Pro.vhf" Line 211: Formal port <Flex_Pin_out_0> does not exist in entity <Papilio_Default_Wing_Pinout>.  Please compare the definition of block <Papilio_Default_Wing_Pinout> to its component declaration and its instantion to detect the mismatch.

 

Having cleaned out the references to old libraries, what could the mismatch be. I am making no modifications to the example.

 

Thanks again for all the help.

 

Howard

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Jack,

 

I found that the component Papilio_Default_Wing_Pinout vhd had the flex connections commented out (this may have been a result of my many thrashings to get a version of the vga test running).

 

I am re compiling without error on the rtl synth.

 

I will see if it works. Not sure if I modified the component, but I do not want to waste your time.

 

Thanks again,

 

Howard

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Jack,

 

Still not sure about the flex commented out. The project built and I got some activity on the   Serial.print(Robot_Control_Library.getPulseCount(0));

function. It looked like it only reads the transitions of one of the encoder inputs(the count changes only after 2 clicks of the rids unit).

 

I put in the following c statements to read the actual I/O of the input pins.

 

  Serial.print("Encoder A is ");              
  Serial.println(digitalRead(4));
  Serial.print("\Encoder B is ");              
  Serial.print(digitalRead(5));

 

My encoder is connected to the AL pins 4 and 5.

 

I get each of the input transitions from 1 to 0 but I only get a count advance/decrement on every 2 transitions

 

 Pulse Count 0: -22865
Encoder A is 0
ncoder B is 1

     Pulse Count 0: -22865
Encoder A is 0
ncoder B is 0

     Pulse Count 0: -22865
Encoder A is 0
ncoder B is 0

     Pulse Count 0: -22865
Encoder A is 0
ncoder B is 0

     Pulse Count 0: -22793
Encoder A is 1
ncoder B is 0

     Pulse Count 0: -22793
Encoder A is 1
ncoder B is 0

     Pulse Count 0: -22793
Encoder A is 1
ncoder B is 1

Not sure if I know enough to dive into the cpp coding. I will probably just read the pins in a loop and decode the count and direction from a SW state machine.

 

Hope this feedback helps others.

 

Thanks again,

 

Howard

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