Myndale

DCMs and static timing

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I'm just starting out with FPGA's so apologies if this is a bit of a noob question but I'm having trouble understanding the relationship between DCM clocks and their effect on static timing.

 

I've designed a circuit to run at 100MHz. If I run it directly off the 32MHz Papilio Pro clock the static timing report states a minimum period of 4.992ns/200.321MHz. However, as soon as I add a DCM to bump the clock up to 100MHz the report drops to 16ns/62.5MHz, even though the circuit itself appears to operate fine at that speed. Furthermore this DCM timing result remains the same even If I strip my design down to a single flip-flop.

 

I'm assuming that either I'm setting something wrong in the DCM core generator or I'm misunderstanding the static timing report (i.e. it applies to the incoming clock, not the DCM output). If the former, can anyone suggest what I might be doing wrong? If the latter, how do I go about testing the maximum frequency of my designs without disconnecting them from the DCM every time?

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Chapter 11 of Hamster's free eBook has a lot of good information about timing on an FPGA:

https://github.com/hamsternz/IntroToSpartanFPGABook/blob/master/IntroToSpartanFPGABook.pdf

 

In my experience that static timing report isn't always accurate. For example, the ZPUino runs with a clock of 96Mhz but like you say, the timing report always gives us a top speed of around 62Mhz. We are obviously running just fine at 96Mhz. I think the best thing is to identify areas of your design that absolutely need to run at a certain speed and then set a speed constraint on that. If that section of your design cannot run at that speed then the whole project will fail to synthesize and you know there is a problem.

 

Jack.

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I think the most important part of the timing report is pass/fail -- either it meets timing (with the clock settings you're using) or it doesn't.  The second most important is, if it meets timing, by how much?  If it fails, where?

 

If it meets timing, but the MHz it lists is below the clock speed you've set up -- I think it's talking about a different clock.  When you've got more than one clock speed on your FPGA, the notion of which one is the "real one" seems ill-defined.

 

If it doesn't meet timing, it still might work.  I've seen it happen.  But I wouldn't count on it.

 

Even where the listed MHz makes sense, it's not an absolute speed limit for your design.  Sometimes I've raised the clock rate a little above that, and rebuilt, and it's made timing even at the higher clock rate.  I think the tools manage to trade off logic size for speed. As I kept raising the clock rate, eventually it failed.  And the timing report told me it failed.

 

I don't think the 62.5MHz means that the 100MHz clock rate you chose is not getting checked.  In the timing report on one of my projects, I see "Requirement: 12.5ns", which corresponds to the 80MHz I set up to get out of the DCM.  On the same report, it lists maximum frequency 62.5MHz.  I think that 62.5MHz is what input clock the DCM itself can handle with the current settings.  When using the oscillator on the Papilio, that's always 32MHz.  In a board under development or a more complicated design, it might vary.

 

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Thanks for the feedback, it looks like I was indeed not understanding the timing report correctly. Time to go hit the docs again.

And thanks for the helpful tip Jack. I've created a double-buffer in BRAM so I can draw one scan line while the previous one is being drawn by my VGA signal generator. My draw circuit is running at 100MHz and I'm using a 2-bit logic vector to down-sample this to 25MHz for my signal generator. Am I correct in the understanding that I can simply put my signal generator in it's own module and give it a 25MHz timing constraint? The fact that I'm generating the 25MHz clock from the 100MHz clock (as opposed to creating a second DCM clock) won't somehow cause problems, will it?

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Hello Myndale,

 

It shouldn't be a problem to use the 2-bit logic vector to make your 25Mhz clock. But having said that, there is a better approach. You are probably using the FX output of the DCM for the 100Mhz clock, you should be able to use the divide output of the DCM to get a 25Mhz clock if I'm not mistaken. If you can't get the correct numbers to do that then you can always use a PLL which has multiple outputs. Or just use the Clocking Wizard and tell it that you want a 25Mhz and 100Mhz clock and let it decide the best way to accomplish that.

 

Jack.

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Thanks Jack, that works fine. Not sure how I missed those multiple output options in the wizard...a case of not seeing the forest for the trees I guess!  :)

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Hi,

 

>> ... If I run it directly off the 32MHz Papilio Pro clock the static timing report states a minimum period of 4.992ns/200.321MHz.

>> However, as soon as I add a DCM to bump the clock up to 100MHz the report drops to 16ns/62.5MHz,

 

is it possible that it tries to tell us it can handle an input clock up to 62.25M?

Originally you were driving with 32M and the limit was 200 M.

Your DCM multiplies the input clock by (approximately) a factor of three, so an input clock of 62.5M would result in the same 200M for the circuit.

Should read the small-print in the timing report, what clock exactly it refers to.

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