Quickstart bit file works but logic analyzer isn't

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Never mind, see UPDATE at the end of the post.


I just rc'vd the Papilio Pro and a 16bit level shifter wing and installed both the loader software and the DesignLab software. The loader works as I've installed the quickstart bit file for the PPro and verified at the level shifter wing it works. ie looked at bit 0 wiggling, pulled bit 1 high(5v) and bit 0 stopped wiggling and was high. Did this for all bits down the wing.


Then I loaded the logic analizer bit file posted in the One-Pro logic analyzer and loaded up OLS first from the DesignLab and used the query button for meta data to see the meta data. It came back as this:


Device type Open Logic Sniffer v1.01 Firmware 3.07 Protocol 2 Ancillary -


So it would seem there are comms. And BTW, I looked at the comms from the QuickStart file by firing up MiniCom and saw the data streaming so I know the ports are working.


Now, I do an acquisition with bit 0 pulled up but don't see any change in the display for any of the 8 bits listed(0-7).


Have I missed something?





I figured out that it's setup for IO connector bank A. I should have known but the wing just looked like it fit/belonged on connector bank C given its single row configuration matched the wing exactly.  Rookie here. It would be great to get it configured to use Connector Bank B since that would put the wing inbound over the board instead of hanging off the side.

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I guess I posted too soon. dropped the acq rate from 200MHz to 100MHz and found bit 0 on the level shifting wing mapped to channel 16( group 2 ) on OLS.  I will look for a way to remap that.



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