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Hardware Verification for AVR8 Soft Core

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Hi,

 

Do you guys know of a reliable open source method to perform hardware verification on the AVR8 Soft core? 

I know using the VHDL code for the AVR8 with Xilinx ISE Web pack software helps us to debug code written in the Arduino IDE, but is there a way to maybe integrate both and automate it?

 

Thanks,

 

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Hi Jack,

 

Thanks for the prompt reply. Let me elaborate. I was looking for an open source method for verifying the AVR8 VHDL code.

 

I was looking to get the VHDL verified using typical free available hardware verification tools. Our next steps will be to come up with a 'hybrid' hw/sw modeling design (e.g., using TSV sw modeling and VHDL formalism) and use the hybrid model for monitoring and intrusion detection. This way when someone writes a program in the Arduino IDE, we can verify that it both the hardware and software are going to do what they are supposed to. It can help us find bugs in the clock mismatch etc. I wanted everything to be open source and to have it automated as far as possible

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Hello, 

 

I've used the free ISIM software from Xilinx to simulate the AVR8 core in the past, you just have to figure out how to import the generated hex file into the simulator. I know its possible but I don't remember how I did it in the past. If you want open source then I think gsim and gwave will do the same? Alvie uses that combination and can maybe chime in.

 

Jack.

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Hi,

 

Yes, I've watched the tutorial.

Thank you for that by the way. It was very interesting.

 

But what I'd really like to do is (make an attempt) at automating the process.

Perhaps the first step would be to determine what would be the exploitable bugs during the verification process so that they can be detected using such a methodology.

 

The end result would be something like what this paper is talking about - http://www.doc.ic.ac.uk/~wl/papers/11/fpt11ks.pdf

They've used Verilog there. I've tried to summarize it below:

 

They employ a two pronged approach using design and verification. In design, an application program (in our case, C code written in the Arduino IDE) will be compiled into machine code. This machine code customizes the instruction set by removing all functionality that is not used. Using the machine code as input, A Processor Generator is employed to customize a soft-processor template (in our case Verilog description of the AVR8 Soft Processor) and generate a customized soft processor design. They therefore generate an optimized system consisting of machine code+soft processor.

 
For verification, they use the formal model of the customized processor, the corresponding machine code model and the assertions about the machine code program and verify that the execution of the machine code on the formal model of the customized processor. meets the functional specification of the high level application program. 
 
If you'd like to understand this process better, please see the diagram and content in section III of the paper. 

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Sure its possible, it will just take some work. The first thing you need to accomplish is automate getting AVR8 code that has been compiled into machine language into the simulation model. I know its possible, I did it years ago, but since it was years ago I don't remember much about what I did to accomplish it... It was back in 2009 when I was trying to get the AVR8 to work on the Papilio in the first place. The Soft Processor was not working at all so I had to compile some code into machine language, load it into the simulator, and then simulate the entire AVR8 with the code loaded. I then compared the generated waveforms to what the AVR simulator did with the code. I eventually discovered that there was a bug with the data2mem tool that would reverse a byte when it encountered a line ending...

 

I did all of this with ISIM, if you want open source then look into using ghdl to simulate the design and +gtkwave to view the resulting waveforms. You will just need to figure out how to pull your code into ghdl and simulate it.

 

Jack.

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Hi,

 

I believe the Xilinx ISE Webpack Software has a free version, so I think I can use ISIM as "freeware".

I think your tutorial from here covers what to do quite well-http://www.gadgetfactory.net/2011/04/tutorial-simulate-avr8-and-custom-cores/

 

Thank you for the romgen source. Do you have some kind of tutorial or read me that would tell me how to use it?

I'm assuming it simulates the ROM of the Arduino for the purpose of the simulation with the AVR8 core.

 

Thanks a lot for your help thus far. 

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Hi Jack,

 

Can you elaborate on how to use romgen?

Also can you tell me more about the problem you had in your comment (#6)? 

 

To actually try and do my project, I need to generate a bad case, i.e. possibly make something not work in the VHDL code for the arduino soft core and then debug it from the simulation. Any advice would be helpful

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Hello,

 

I'm really sorry, but it was over six years ago that I did that work... I really don't remember details anymore...

 

Here is a forum thread discussing a fix for the bug I encountered in #6. 

http://forum.gadgetfactory.net/index.php?/topic/1146-issues-with-srec-cat/?hl=data2mem

Here is a more detailed guide with more info from Hamster:

http://forum.gadgetfactory.net/index.php?/topic/1153-a-big-boring-tutorial-on-how-to-get-programs-into-your-papillo-one/

 

There is no tutorial or docs that I know of for romgen. I had to learn from the source code.There are several romgen examples in the Papilio Arcade sources:

https://github.com/GadgetFactory/Papilio-Arcade/blob/master/pacman_rel004_sp3e_papilio/scripts/build_roms_pacman.bat

 

Jack

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