briano

Unknown Papilio Board

41 posts in this topic

Why did this thread die on the 22nd of November 2015?? Has there been no problems with the software ?

Following the software loading instructions does not work. XILINX hangs on the download helper. How do I get the software?

Has anyone actually tried to follow the instructions recently?

I am using win 10.

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I also get unknown board. I just got my Papilio Duo 2048MB  and am using DesignLab 1.0.7 on lubuntu 14.04.  When I try to download the code, I get the following:

 

Executing  /home/bn/sandbox/DesignLab-1.0.7/hardware/tools/zpu/bin/zpu-elf-size /tmp/build6380494414156111291.tmp/Hello_World.cpp.elf
Binary sketch size: 7,840 bytes (of a 2,048,000 byte maximum) - 6,448 bytes ROM, 2,484 bytes memory, 0% used

Sketch uses 5,356 bytes (0%) of program storage space. Maximum is 2,048,000 bytes.
Global variables use 1,092 bytes of dynamic memory.
Board: Unknown board @ 96000000 Hz (0xa4051300)
Board mismatch!!!.
Board is:      0xa4051300 'Unknown board'
Sketch is for: 0xb4051300 'Unknown board'

 

When I execute dmesg after I plug in the board, I see the following:

 

[ 3708.757131] usb 2-3: FTDI USB Serial Device converter now attached to ttyUSB0
[ 3708.758746] ftdi_sio 2-3:1.1: FTDI USB Serial Device converter detected
[ 3708.758828] usb 2-3: Detected FT2232H
[ 3708.758835] usb 2-3: Number of endpoints 2
[ 3708.758841] usb 2-3: Endpoint 1 MaxPacketSize 512
[ 3708.758847] usb 2-3: Endpoint 2 MaxPacketSize 512
[ 3708.758853] usb 2-3: Setting MaxPacketSize 512
[ 3708.759212] usb 2-3: FTDI USB Serial Device converter now attached to ttyUSB1

 

 

I can see the LED blinking about once a second, so the board is alive.

 

  What should I do?

 

Thanks,

Blake

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If I "load circuit" before "upload", the circuit appears to get programmed correctly, and the result of the upload is:

 

sketch uses 5,356 bytes (0%) of program storage space. Maximum is 2,048,000 bytes.
Global variables use 1,092 bytes of dynamic memory.
Board: Unknown board @ 96000000 Hz (0xb4051300)
Programming completed successfully in 0.56 seconds.

 

And the program appears to run correctly.

 

Blake
 

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Hello Blake, 

 

Sorry for the late response, things got really hectic the last couple of days. But it sounds like you found the problem. Basically you had an old version of ZPUino running on your Papilio board and you just needed to load the circuit that was associated with the sketch you were running to get everything matching up.

 

Jack.

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Hi Newbie

I am Windows 10 users.

DesignLab for Windows ran well.

Try this attach the code?

Please change for original script file.

C:\DesignLab-1.0.7\hardware\tools\papilio\papilio_loader\Plapilio_Programmer.sh

-> changed -> Papilio_Programmer.sh

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Good afternoon everyone,

It seems I am having something close to the issue that some of these posters are reporting.

 

I have the 2mb duo, which I ordered and received back in May of 2016. I have been unable to get back to tinkering with things until today.

Currently, I am using windows 10. Designlab 1.0.7. Downloaded today installed, and appears to be working.

 

 

I can see my duo in device manager and in designlab (Papilio duo FPGA serial port) as com6.

My power switch is down (FPGA). power light is on. SW1 is down (though I have tried in both positions with no difference detected).

The Rx light is flashing and the serial monitor in designlab is showing the ASCII table display program.

The one second on one second off led blink on pin 13 is running.

 

I have been trying to follow the designlab quickstart tutorial.

Everything works right up to the "Load the circuit" step, which, when pressed results in a slight delay of maybe a minute or so before throwing this:

"

C:\Programming\DesignLab-1.0.7/hardware/tools/papilio/papilio_loader/Papilio_Programmer.bat C:\Programming\DesignLab-1.0.7\libraries\ZPUino_Vanilla\circuit\DUO_LX9\papilio_duo_lx9.bit 
Programming to SPI Flash                  

---- this is where the delay occurs ----

This application has requested the Runtime to terminate it in an unusual way.
Please contact the application's support team for more information.
Using devlist.txt
readusb: Timeout readusb
terminate called after throwing an instance of 'io_exception'
Unknown Papilio Board
 "

Now, after trying several different things, including install/reinstall of the designlab software (twice actually using a total of 3 different directory structures all with the same results) I went ahead and tried doing the compile/upload where I received this wall of error text. (there were also an error or two buried deeply in the compile process, no hope of finding them in the mountain of compile messages I am sorry, I tried scrolling to find them, but was unsuccessful).

"C:\Programming\DesignLab-1.0.7/hardware/tools/zpu/bin/zpuinoprogrammer.exe -s 1000000 -R -v -v -v -v -d COM6 -b C:\WINDOWS\TEMP\build5565587890952040738.tmp/Papilio_DUO_QuickStart.cpp.bin 
Connecting...
[1473197305.047593] Tx: 0x7e 0x01 0x1e 0x0e 0x7e
Rx: 0x81 0x01 0x09 0x06 0x00 0x00 0x07 0xef 0x80 0x05 0xb8 0xd8 0x00 0xa4 0x05 0x13 0x00 0x44 0xc0 0x7e
Got packet size 17
Got programmer version 1.9
SPI offset: 393216
CODE size: 520064
Board: Unknown board @ 96000000 Hz (0xa4051300)
[1473197305.058622] Tx: 0x7e 0x02 0x2c 0x95 0x7e
Rx: 0x82 0xc2 0x20 0x17 0x00 0x75 0x58 0x7e
Got packet size 5
SPI flash information: 0xc2 0x20 0x17, status 0x00
Detected MX25L6445E flash
Will program sector 6 (page 1536), original offset 0x00060000
Need to program 7236 7424 bytes (29 pages)
Reading data, 7232 bytes
Board mismatch!!!.
Board is:      0xa4051300 'Unknown board'
Sketch is for: 0xb4051300 'Unknown board'

"

Can anyone offer some suggestions? it's kind of frustrating that everything seems to be working, including my USB connections because I can see the board, and I am getting the ascii program display, but it keeps saying in essence, you have the wrong board connected? This is what I bought :)

Thanks.

Bob

 

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Hello Bob,

Thank you for trying out the Papilio FPGA board. It sounds like the crux of all your problem is that loading a circuit to your FPGA is not working properly. Once we get that resolved then everything should start working.

It sounds like it is a Windows 10 driver issue...

Please take a look at this video and see if it gets your drivers sorted out.

Jack.

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thank you for the quick response sir,

I thought we were on to something there. I followed the steps, right up until the "generic usb" converter was supposed to be there. My system, (always having to be difficult it seems) did not come up with a generic spot in the USB controllers section. I was lucky enough to get "Other Devices" with Papilio Duo with a blue question mark over the icon and then the deathly yellow black exclamation point warning. :/

So, I tried some removals/deletes/installs/reinstalls/search for drivers and all the usual and got back to where I started with... broken but working. Tantalizing and frustrating.

Anything else in your bag of tricks aside from format c: which is always tempting.

Bob

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Darn,

When the driver acts up like this it really is frustrating because I have not been able to find a 100% bullet proof solution. It usually just seems to start working but we have never been able to pin down a solution that works every time... Can you try to disable digital driver signature verification and then re-install the drivers and see if that works? The other thing that seems to make a difference sometimes is to use FTDI's uninstall tool to completely uninstall everything and then install the latest FT2232 drivers from FTDI and the Papilio drivers... I'm sorry for the hassle with all of this, I'm this close to redesigning the Papilio boards without the FTDI chips over this...

Keep us posted,

Jack 

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Success!! Huzzah!!

Thank you sir, That was exactly the process I had to follow.

Uninstall the duo drivers.

Uninstall the FTDI drivers (used the CDM uninstall unitility from their website)

Install the duo drivers (I did them individually from the device manager rather than the driver batch file in the folder)

Install the latest FTDI driver (used the GUI installer they provide, though it really doesn't do much to need a GUI).

Started Designlab 1.07. Went to the duo link in the welcome sketch, as you specified in the tutorial video, did the load ... AND it worked, HUZZAH!

then did the compile/upload and that worked too! hurray again! happily counting away on my tera term monitor. Nice :D

Thank you so much.

Now, I just have to find an idiots guide to FPGA's for dummies and I am golden. 

 

side note:

of course a side effect. Now my bus pirate and usbtiny no longer communicate through avr studio 7 to the chips on my development board for another project that was working. fun with electronics... always something exciting. :facedesk:

 

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Thanks again Jack,

I appreciate the time and patience. I have my usbtiny working again, though bus pirate refuses to communicate to my avr through atmel studio. Self diagnostics and display on the terminal program for the BP work just fine. Anyway, not your problem, I know. Just thought I would share some of the fall out.

As an aside I appreciate the references, thank you. I was trying to find something for the ISE design suite, which, I found from purchasing Mr. Romano's book. So far, I am not to thrilled with this book. I really really wanted to be, but, I am hitting problem after problem using that book. I keep getting frustrated with it, putting it down, investigating other avenues, coming back to it, restarting at the beginning and failing again. Also, I know, not your problem. It's my lack of ... competence, insight, knowledge, something. So, I have been looking, and I will continue to do so.

Anyway, thank you again. it is very much appreciated.

Have a great day sir,

Bob

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My gripe about most HDL guide books is that they very often have misleading, confusing and sometimes completely incorrect statements about the language, and the David Romano book mentioned above is a typical example.  Rather than explaining the language in the context of how it was originally intended to be used (i.e. a language for logic simulation) it is often instead explained in the context of logic synthesis (i.e creating real hardware).  Logic synthesis did not exist when VHDL or Verilog was created, if came later when companies like Synopsys realized that it's possible to create hardware design files from the HDL code BUT only if you use a small subset of the language and use code templates for common structures so that the synthesis process can easy translate it to real hardware.  The HOWTO books then describes this small subset and the templates for synthesis as the definition of the language and it makes it very hard for a beginner to understand why the language is defined as it is.  By focusing on simulation instead of synthesis it's much easier to understand why the language looks like it does - it's defined to make simulation as easy as possible, not to make synthesis as easy as possible.

Here is a case from the David Romano book to illustrate what I'm talking about.  Here is what the book says about the Verilog always block:

Example 3-3. Syntax of always block
always @(sensitivity_list)
begin
//one or more procedural assignment
//statements
end

This is completely incorrect - this is not the Verilog syntax of the always block, this is the synthesis template for combinatorial logic!  The concept sensitivity_list is not mentioned in the IEEE standard, it's made up by people looking at Verilog code from synthesis viewpoint.

The correct IEEE Verilog definition of the always block is this:

always <statement> where <statement> can be a long list of things including delays (#) and event control (@).

For instance, this is legal (but maybe not possible to synthesize):

always
begin
  @ (posedge test) a = 0;
  @ (negedge test) a = 1;
end 

It's easy to explain what happens here if you look at it from the simulator's viewpoint.  The always block is like the loop() statement in Arduino - the simulator will process the statements in the always block forever, when it gets to the bottom it will start again from the top.   The @() part is called event control, the simulator will stop and wait for the event, in this case it will wait for the signal test to have a rising edge.  It will then set a = 0 and continue to the next line which is another event control.  The simulator will pause until test have a falling edge and then it will set a = 1;  This will be repeated forever.  Easy if you look at it as a simulator.

The synthesis template for a D flip-flop looks like this:

always @ (posedge clk)
 q <= d;

and it's easy to see that from the simulator's viewpoint this will simulate a D flip-flop - the simulator will wait for the event rising edge of clk, then set the signal q the same as d.  This will be repeated forever.

Magnus

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Excellent post Magnus, thank you very much for bringing that up. It is something that really tripped me up when I was first learning HDL. Most books that I was reading don't bother to tell you the history, which is a critical piece of information here. It's important to know that VHDL/Verilog started out for simulation and then were later adapted for synthesis. When you are doing synthesis you have to use a subset of the language and you have to common structures to implement the underlying digital structures that you want. Magnus said it very nicely in his post above...

What really helped me was to start with Digital Logic books so I understood the basic building blocks that could be used. Then when it came time to solve a problem figure out how to solve it with the basic building blocks and then how to use HDL to implement those building blocks. The book that finally gave me my "ah ha" moment was this one:

Essential VHDL: RTL Synthesis Done Right

Bob, maybe that is more along the lines of what you are looking for?

Magnus, do you have any other book recommendations?

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To follow up on the code example, I did complete it as a module and ran it through ISE.  The syntax checker said no errors but when I tried to synthesize the module I got this error:

ERROR:HDLCompiler:608 - "test.v" Line 16: Multiple event control statements in one always/initial process block are not supported in this case.

In other words, it's valid syntax but can't be synthesized.

I also did the code for a flip-flop using the same code style to emphasize that always is a keyword by itself:

always
  begin
    a = 0;
    @ (posedge clk) q <= ~q;
  end

and it had no problem synthesize the code.

Magnus

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21 hours ago, mkarlsson said:

...

For instance, this is legal (but maybe not possible to synthesize):

always
begin
  @ (posedge test) a = 0;
  @ (negedge test) a = 1;
end 

...

Thanks! Never looked at it this way. The construct actually seems very useful for testbenches, e.g. dump bus transactions to file when a valid strobe goes high.

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