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SoundBlaster FM HDL

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Pacedev is open source IIRC, I've been in contact with the owner off and on discussing FPGA related things. The forum was still down last I checked but I did get him to bring the repository back up. If it's gone now I did clone the whole thing so I could post it elsewhere.

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It looks to me like the code on OpenCores is more complete even though it specifically calls out the OPL2 as not fully working

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I'm not familiar with DesignLab, but I assume it uses ISE/XST as the underlying synthesizer as you would be targeting the Spartan 6. As ISE/XST doesn't support the newer SystemVerilog features the code will have to be back-ported to Verilog2001, but that should be fairly easy. The only device specific construct in the code is the MMCM, which will have to be regenerated for the Spartan and the clock frequency of the external clock on the board.

 

If the design doesn't fit the Spartan, you could pretty easily trim off the second bank of registers and essentially have an OPL2.

 

The last sort of difficult part would be porting the CPU interface to whatever you are using on that board. But definitely doable.

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The DesignLab format is pretty much just making your core Wishbone compatible and then we convert it to schematic format and concatenate all of the Wishbone signals together to make it easy to connect in the schematic editor.

 

Yes, it is indeed using ISE/XST for synthesis on the Spartan 6. So if you are willing to make your core fit (OPL2) and give it a Whishbone interface then I can do the rest to bring it into DesignLab so people can then use it with the RetroCade synth!

 

Does that sound good?

 

Thanks!

Jack.

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Sounds like a great project for someone with motivation. I'll help out as much as I can but this is a decently substantial project that I don't have time for. I bet someone in your user base has the know how and motivation to do this.

 

Another alternative to converting to Verilog... if someone has access to Synopsis Synplify, they could generate a netlist with the existing SystemVerilog that could be imported by ISE. Orrr, sounds like you guys are VHDL people so just convert to that. As VHDL people you're already used to lots of typing! :)

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Thanks for the link. Interesting read.

So they use sin(x)*a = exp(log(sin(x)) + log(a)), with ROMs for log(sin(x)) and exp(), avoiding the multiplication with the envelope.

Interesting that 8 bit phase resolution is enough.

 

I still own my first two synths, Korg 707 and Yamahaha DX7 II, the former being a clone of the latter with improved aerodynamics...

FM rules, even if it sounds horrible :D I used the 2x6 operators mainly for additive synthesis as wannabe fake Hammond organ.

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Well, just to clarify, frequency resolution is 20 bits or about 0.047Hz, determined by the width of the phase accumulator and the sample rate. The phase input to the ROMs is truncated as is typical with NCOs but this doesn't affect the frequency accuracy. Even though the input to the sine ROM is 8 bits, phase resolution is actually 10 bits, as only a quarter of the sine wave is stored and symmetry used to translate it to all 4 quadrants. But yes this truncation does cause periodic phase error that typically shows up as spurious products in the frequency domain. Not sure if they're audible.

 

Yeah the OPL3 has some additive synthesis modes too.

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>> phase resolution is actually 10 bits,

 

good point.

I was just surprised that this works with such simple hardware. Artifacts are part of the sound :)

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