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Questions about Sump Blaze Logic Analyzer

22 posts in this topic

Hi,

 

I looked at the "Benchy_Sump_LogicAnalyzer" example. If I understand it correctly, the serial input/output of the "Sump Blaze Logic Analyzer x8" symbol goes to the ZPUino, and on the ZPUino there runs a sketch that forwards the serial IO to the serial port of the Papilio DUO board.

 

Is it necessary to forward the data through the ZPUino, or can the logic analyzer be used in a design that doesn't have one? I tried to add the logic analyzer to a simple design of my own and connected the tx and rx pins of the logic analyzer to the TXD and RXD pins of the Pailio DUO. Then I tried to connect to it with Logic Analyzer GUI, but that didn't work so far. I tried device types "Original SUMP device" and "Papilio Logic Analyzer", and when I click "Show device metadata" I see the serial LEDs blinking on the Papilio board, but then the "Device type" is cleared and nothing is retrieved.

 

And for my understanding who the logic analyzer works: I looked at the VHDL implementation of the logic analyzer, and I can't find any actual logic in there, just lots of mappings and constant definitions. Is this really the whole implementation, or are there additional modules involved that I was not able to find?

 

Thanks

Stephan

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And for my understanding who the logic analyzer works: I looked at the VHDL implementation of the logic analyzer, and I can't find any actual logic in there, just lots of mappings and constant definitions. Is this really the whole implementation, or are there additional modules involved that I was not able to find?

Answer to myself: When the "BENCHY_sa_SumpBlaze_LogicAnalyzer8.vhd" is added to the design, it pulls in a lot of VHDL files that contain the actual implementation of the logic analyzer.

 

When I try to add the logic analyzer to one of my play designs for the Papilio DUI, I get the following error when compiling the design:

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock   IOB component <CLK> is placed at site <P94>. The corresponding BUFG component   <XLXI_63/Inst_clockman/clkin2_inst> is placed at site <BUFGMUX_X2Y3>. There   is only a select set of IOBs that can use the fast path to the Clocker   buffer, and they are not being used. You may want to analyze why this problem   exists and correct it. If this sub optimal condition is acceptable for this   design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to   demote this message to a WARNING and allow your design to continue. However,   the use of this override is highly discouraged as it may lead to very poor   timing results. It is recommended that this error condition be corrected in   the design. A list of all the COMP.PINs used in this clock placement rule is   listed below. These examples can be used directly in the .ucf file to   override this clock rule.   < NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; >ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

P94 is the pin where the 32Mhz oscillator is connected to the Spartan FPGA, so that cannot be changed. I don't understand yet where the placement of the BUFG component at site BUFGMUX_X2Y3 comes from, and where it could be modified. Is this a known issue with the logic analyzer?

 

Thanks

Stephan

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Hello Stephan, 

 

Can you zip up your project and post it here? I'll take a look on Monday.

 

Jack

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Hello Jack,

 

thanks for taking a look. The project is attached.

 

Should it be possible in general to use the logic analyzer without forwarding the serial port through the ZPUino?

 

Stephan

divider.zip

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Stephan,

 

For sure, I'm certain I've done that before. I might need to change the clock input buffers for it to work correctly. I want to improve the logic analyzer library this week and expose all 32 channels and maybe make one attached to the SRAM for the DUO.

 

Jack.

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Hello Stephan,

 

The problem you are running into is that GCLK input pins (like the one that the Oscillator on the Papilio board is connected to) can only feed into BUFG primitive's that are in the same bank as the input pin. Xilinx ISE doesn't do a very good job of automatically connecting GCLK pins to BUFG pins that are in the same bank and it ends up connecting it to a BUFG in a different bank when it needs to connect a GCLK input pin to multiple BUFG's. BUFG's serve to connect a clock input from a clock source such as GCKL pin or a DCM or PLL to the global routing infrastructure.

 

The best approach is to never connect a GCLK pin to more then one clock source because ISE gets confused. In your circuit you have the GCLK pin (the clk I/O Marker) connected to the clock divider and the logic analyzer. The tools automatically add an IBUF (clock input buffer) which then feeds to the clock divider (I think the tools add a BUFG here too but am not sure) and the logic analyzer which has a BUFG feeding into a DCM in the source code. It looks like this:

post-29509-0-00203900-1428359756_thumb.p

 

This seems to confuse the tools and causes CLK (the GCLK) to be connected to a BUFG in a different zone which gives this error message:

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock   IOB component <CLK> is placed at site <P94>. The corresponding BUFG component   <XLXI_63/Inst_clockman/clkin2_inst> is placed at site <BUFGMUX_X2Y3>. There   is only a select set of IOBs that can use the fast path to the Clocker   buffer, and they are not being used. You may want to analyze why this problem   exists and correct it. If this sub optimal condition is acceptable for this   design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to   demote this message to a WARNING and allow your design to continue. However,   the use of this override is highly discouraged as it may lead to very poor   timing results. It is recommended that this error condition be corrected in   the design. A list of all the COMP.PINs used in this clock placement rule is   listed below. These examples can be used directly in the .ucf file to   override this clock rule.   < NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; >

What seems to prevent this from happening is to be careful to only connect clk to a single symbol at a time. Then feed the clock input from the IBUF out to a FPGA signal which can then feed other BUFGs, DCMs, PLLs, or FPGA logic. I'm attaching a new copy of the papilio_clocks.vhd file that defines the papilio_clocks "chip". This updated version connects CLK_32Mhz to a signal and allows it to be fed into other components without errors.

 

Please replace your libraries/Building_Blocks/papilio_clocks.vhd file with the attached one. I will include the upgrade in DesignLab 1.0.6 release.

 

With this new file you can setup your circuit like this:

post-29509-0-41155200-1428360104_thumb.p

 

Notice that clk feeds into a single chip that generates multiple clocks and passes the clk_32Mhz through as a signal instead of a straight IBUF which seems to make the tools work right. 

 

So the important thing is that we always need to be careful to only connect the clk IO marker to a single chip...

 

I've verified that the circuit in the picture works, but I had to set the Logic Analyzer client to 10Khz to see anything.

 

Hope this helps,

Jack.

papilio_clocks.vhd

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Hello Jack,

 

thanks for tracking this down. I can confirm that after replacing the papilio_clocks.vhd with the new version and after modifying the design as proposed the design is compiled successfully.

 

What I still failed to do is to capture anything after uploading the bit file to the board. How did you start the capturing process? I tried several Device Types in the OLS capture settings dialog after setting the Sampling Rate on the Acquisition tab (see screen shots).

 

I tried "Open Bench Logic Sniffer", "Original SUMP device" and "Papilio Logic Analyzer". The capture starts, and when I stop the capture it always says "Capture failed! null" in the lower left corner of the main window. When I start the capture and when I stop the capture I see the Tx and Rx LEDs flashing on the Papilio DUO board.

 

Sorry, lots of questions...

 

Thanks

Stephan

 

 

post-38585-0-70282700-1428361998_thumb.p

post-38585-0-15391600-1428362000_thumb.p

post-38585-0-37047700-1428362442_thumb.p

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What I still failed to do is to capture anything after uploading the bit file to the board. How did you start the capturing process? I tried several Device Types in the OLS capture settings dialog after setting the Sampling Rate on the Acquisition tab (see screen shots).

 

I tried "Open Bench Logic Sniffer", "Original SUMP device" and "Papilio Logic Analyzer". The capture starts, and when I stop the capture it always says "Capture failed! null" in the lower left corner of the main window. When I start the capture and when I stop the capture I see the Tx and Rx LEDs flashing on the Papilio DUO board.

 

After playing some more with the Acquisition options it suddenly worked! The problem was that I had set the Recording Size to "Automatic (maximum)", and I always stopped the capturing manually. Probably I didn't wait long enough.

 

After setting the Recording Size to a fixed amount it works now.

 

Stephan

post-38585-0-18157400-1428363542_thumb.p

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Here is a video of what I'm doing:

 

 

Just saw your new reply - when you set the sampling rate so low, at 10,000 Hz and the Recording size is big then it will take forever to sample...

 

Jack.

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Here is a video of what I'm doing:

 

 

Just saw your new reply - when you set the sampling rate so low, at 10,000 Hz and the Recording size is big then it will take forever to sample...

 

Jack.

Yes, my fault. I had thought that I can just stop the capturing with the red button when I like.

 

Thanks for the video walk through. Hopefully it will help others to get started with the logic analyzer.

 

Stephan

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Hello Jack

 

With this new file you can setup your circuit like this:

attachicon.gifgood clocks.png

 

Where do the RXD and TXD marker connect to? (Arduino_0 and Arduino_1? Did you change the COM port used in the example video?)

 

I need to have a Logic Analyzer in my ds1wm design for testing and debugging. Thus I had a look at the Benchy_Sump_LogicAnalyzer example. It uses a COMM_zpuino_wb_UART to connect the logic analyzer to the zpuino together with some code that forwards the serial data to and from USB serial port. The problem is that I need the same USB connection (from zpuino) to print debug data to console/monitor. So the question is how to connect the logic analyzer to the ATmega Serial1 port (and use it's USB serial connection) instead? Is ATmega Serial1 fast enough? Is such a connection established by using RXD and TXD? What physical connection/pin do RXD and TXD utilize?

 

Thanks and Greetings

DrTrigon

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Hello DrTrigon,

 

Please take a look at the JTAG Logic Analyzer project, it is meant for scenario's like you describe where you need the rx and tx pins for the design you are debugging. The JTAG Logic Analyzer option will use a special bridge that runs on your computer that will turn the first channel of the FTDI chip that is connected to the JTAG port of the FPGA into a serial communication channel that the Logic Analyzer client can connect to. 

 

I use this option regularly when I am debugging the ZPUino and it works pretty well. The only caveat is that I've only included the application that needs to run on your computer for the Windows version of DesignLab... Are you using Windows or Linux?

 

Jack.

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Please take a look at the JTAG Logic Analyzer project, it is meant for scenario's like you describe where you need the rx and tx pins for the design you are debugging. The JTAG Logic Analyzer option will use a special bridge that runs on your computer that will turn the first channel of the FTDI chip that is connected to the JTAG port of the FPGA into a serial communication channel that the Logic Analyzer client can connect to. 

 

I had a short look and from that as well from what you describe, I think that is the solution to my question - I will test this as soon as possible! Thanks!

 

Though just out of curiosity; would the solution I proposed before work as well? ;)

 

I use this option regularly when I am debugging the ZPUino and it works pretty well. The only caveat is that I've only included the application that needs to run on your computer for the Windows version of DesignLab... Are you using Windows or Linux?

 

Good point; I'm running Linux. Parts of the reason why I love the Papilio DUO so much is it's Linux compatibility. :)

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I think what you are proposing should work. You just need to connect the rx and tx lines of the Logic Analzyer to the pins that the serial pins of the AVR chip. Then on the AVR chip you will need to run a little sketch that will forward the data from the serial port to the USB port. I think USB is on serial0 and the serial pins are serial1. It should be fast enough to work just fine and this is probably an easier solution to accomplish under Linux.

 

Let us know how it works.

 

Jack.

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Hello Jack!

 

What's the plan about a release of a linux solution for the JTAG server and Logic Analyzer client software? What is "Coming soon"? :)

 

I had a look for linux JTAG servers, I found; Altera and UrJTAG (last update 2009) - so I don't know what to do here right now.

 

I think what you are proposing should work. You just need to connect the rx and tx lines of the Logic Analzyer to the pins that the serial pins of the AVR chip. Then on the AVR chip you will need to run a little sketch that will forward the data from the serial port to the USB port. I think USB is on serial0 and the serial pins are serial1. It should be fast enough to work just fine and this is probably an easier solution to accomplish under Linux.

 

I tried to use the RXD and TXD markers, like:

 

post-39148-0-49617300-1452370934.png

 

which resulted in 2 mapping errors:

 

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=P46) which requires the combination of the symbols listed
   below to be packed into a single IOB component.

   The directed pack was not possible because: More than one pad symbol.
   The symbols involved are:
       BUF symbol "RXD_IBUF" (Output Signal = RXD_IBUF)
       PAD symbol "RXD" (Pad Signal = RXD)
       PAD symbol "ext_pins_in<2>" (Pad Signal = ext_pins_in<2>)
ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=P141) which requires the combination of the symbols listed
   below to be packed into a single IOB component.

   The directed pack was not possible because: More than one pad symbol.
   The symbols involved are:
       BUF symbol "TXD_OBUF" (Output Signal = TXD)
       PAD symbol "TXD" (Pad Signal = TXD)
       PAD symbol "ext_pins_out<25>" (Pad Signal = ext_pins_out<25>)

 

so I went for the Arduino pin markers as:

 

post-39148-0-23978100-1452371014.png

 

which synthesized well.

 

Next I will run a sketch like the Arduino Mega serial example code (very similar to

the Benchy_Sump_LogicAnalyzer sketch) in order to forward the serial data as

mentioned. Will keep you informed...

 

Thanks for your help and Greetings

post-39148-0-49617300-1452370934.png

post-39148-0-23978100-1452371014.png

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Hey, sorry for the slow reply. I got this message on my phone over the weekend and couldn't respond properly at that time...

 

Ok, so for more information about the JTAG server please take a look at this post:

http://forum.gadgetfactory.net/index.php?/topic/1905-jtag-logic-analyzer/?hl=jtag

 

It is just a modified version of papilio-prog so it should run under Linux just fine. You can download the source and compile it for yourself if you like.

https://github.com/GadgetFactory/Papilio-Loader/tree/debugMode

https://github.com/GadgetFactory/Papilio-Loader/commit/1af6ec49021e9466d868fab87beae909c6d0f4a6

 

For the other approach of using the rx/tx version of the Logic Analyzer, please take a look at the following project, you can find it in the Table of Contents:

Stand Alone Logic Analyzer
This is the "Sump" Logic Analyzer that is used in the Open Bench Logic Sniffer. Use this to make a standalone logic analyzer that is directly connected to the Papilio serial port. Sample at speeds up to 200Mhz!
example://Benchy_Sump_LogicAnalyzer/Benchy_Sump_LogicAnalyzer.ino
 
It has code to forward the serial port, you should be able to run that code on the AVR chip to get this to work...
 
Let me know how it works.
 
Jack.

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Hey, sorry for the slow reply. I got this message on my phone over the weekend and couldn't respond properly at that time...

 

;)) I exactly know this problem...

 

Ok, so for more information about the JTAG server please take a look at this post:

http://forum.gadgetfactory.net/index.php?/topic/1905-jtag-logic-analyzer/?hl=jtag

 

It is just a modified version of papilio-prog so it should run under Linux just fine. You can download the source and compile it for yourself if you like.

https://github.com/GadgetFactory/Papilio-Loader/tree/debugMode

https://github.com/GadgetFactory/Papilio-Loader/commit/1af6ec49021e9466d868fab87beae909c6d0f4a6

 

Oh... cool! Thanks for the links, I had a look at it - this is what I did:

-    int sin_size;    

+    socklen_t sin_size;    

 

in order to solve:

progalgspi.cpp:995:69: error: invalid conversion from ‘int*’ to ‘socklen_t* {aka unsigned int*}’ [-fpermissive]

   connected = accept(sock, (struct sockaddr *)&client_addr,&sin_size);

  • then follow instructions in .../Papilio-Loader-debugMode/papilio-prog/README:

$ sudo apt-get install git autogen automake g++ libftdi-dev

$ ./autogen.sh

$ ./configure && make

 

after that I had a binary called .../Papilio-Loader-debugMode/papilio-prog/papilio-prog (not butterflyprog as mentioned in the README).

 

So first thing is to check whether it runs:

$ ./papilio-prog -h

Usage:./papilio-prog [-v] [-j] [-f <bitfile>] [-b <bitfile>] [-s e|v|p|a] [-c] [-C] [-r] [-A <addr>:<binfile>]

   -h            print this help

   -v            verbose output

   -j            Detect JTAG chain, nothing else

   -d            FTDI device name

   -f <bitfile>        Main bit file

   -b <bitfile>        bscan_spi bit file (enables spi access via JTAG)

   -s [e|v|p|a]        SPI Flash options: e=Erase Only, v=Verify Only,

                       p=Program Only or a=ALL (Default)

   -c            Display current status of FPGA

   -C            Display STAT Register of FPGA

   -r            Trigger a reconfiguration of FPGA

   -p            JTAG passthrough mode

   -a <addr>:<binfile>    Append binary file at addr (in hex)

   -A <addr>:<binfile>    Append binary file at addr, bit reversed

Ok, yes it runs and comparing this part of the binary against .../DesignLab-1.0.7/tools/papilio-prog-jtag-server/papilio-prog-jtag-server.exe gives me the impression these are the same programs, right?

Now the question to me is how to use this binary? From the links you posted I would be temped to run the -p (passthrough mode) but from the Benchy_Sump_LogicAnalyzer_JTAG example, I would think I have to run it without parameters:

     For Windows: tools://papilio-prog-jtag-server/papilio-prog-jtag-server.exe

 

For the other approach of using the rx/tx version of the Logic Analyzer, please take a look at the following project, you can find it in the Table of Contents:

Stand Alone Logic Analyzer
This is the "Sump" Logic Analyzer that is used in the Open Bench Logic Sniffer. Use this to make a standalone logic analyzer that is directly connected to the Papilio serial port. Sample at speeds up to 200Mhz!
example://Benchy_Sump_LogicAnalyzer/Benchy_Sump_LogicAnalyzer.ino
 
It has code to forward the serial port, you should be able to run that code on the AVR chip to get this to work...

 

Thanks for this hint, are you referring to the Benchy_Sump_LogicAnalyzer_Standalone example? Here I am a bit confused by 2 things:

  • Here the markers used are called "rxd" and "txd". How are they related to "RXD" "TXD"? This boils down to the question of what serial port gets used?
  • The code does no serial forwarding. Again what serial port is used? The FPGA one? For me this one is occupied by ZPUino, right?

Thanks a lot!

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Hello,

 

Yes, I think you are going to want to do -p for JTAG passthrough mode. It should come back and tell you what port it is listening on... I think the version you compiled is a newer version then the one I included with DesignLab for the Windows side. With the newer version I added the -p option to papilio-prog instead of hardcoding the functionality into the app...

 

For the Benchy_Sump_LogicAnalyzer_Standalone example:

 

I'm not sure we are seeing the same thing... This is what the circuit should look like:

post-29509-0-29293000-1453138784_thumb.p

 

There should be a second UART connected to Wishbone slot 5 and then instantiated in the code like this:

HardwareSerial mySerial1(2);  //This finds the second instance of a serial port - in our case connected to wishbone slot 5

rxd and txd are not connected in this circuit. Instead we have the normal behavior for a ZPUino design, the rxd and txd pins are connected through the ext_pins_in and ext_pins_out bus and they are the usual Serial object.

 

To forward all data from the 2nd UART that we connect to Wishbone slot 5 and then to the SUMP logic analyzer we use the following code:

HardwareSerial mySerial1(2);  //This finds the second instance of a serial port - in our case connected to wishbone slot 5void setup() {  // put your setup code here, to run once://  delay(3000);    Serial.begin(115200);  mySerial1.begin(115200); }void loop() {  // put your main code here, to run repeatedly:   if (mySerial1.available()) {   Serial.write(mySerial1.read());   }  if (Serial.available()) {   mySerial1.write(Serial.read());   }  }

Serial is the USB serial port and mySerial1 is the serial port we connect to Wishbone slot 5 and the Logic Analyzer core. 

 

Your use case is going to be different, but the code that would run on the AVR chip would be similar. According to the Arduino page the Serial ports should work like this:

 

 

 

Separation of USB and serial communication.

On the Leonardo and Micro, the main Serial class refers to the virtual serial driver on the board for connection to your computer over USB. It's not connected to the physical pins 0 and 1 as it is on the Uno and earlier boards. To use the hardware serial port (pins 0 and 1, RX and TX), use Serial1. (See the Serial reference pages for more information.)

 

You want to connect the rx and tx of the Sump logic analyzer to the hardware serial port of the AVR chip which is on pins 0 and 1 using a circuit on the FPGA like you have already done. Then you want to forward the input and output from the hardware serial port, Serial1, to the USB serial port which is the first serial port, Serial. You do that with a sketch like like this running on the AVR chip:

void setup() {  // put your setup code here, to run once://  delay(3000);    Serial.begin(115200);  Serial1.begin(115200); }void loop() {  // put your main code here, to run repeatedly:   if (Serial1.available()) {   Serial.write(Serial1.read());   }  if (Serial.available()) {   Serial1.write(Serial.read());   }  }

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That should then have the output from the Sump Logic analyzer going out through the AVR chips USB port...

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Hello Jack!

 

Thanks for your detailed answers! Sorry for not answering - I had a busy time, then holidays and meanwhile a few quadrocopters arrived... ;))

 

For the Benchy_Sump_LogicAnalyzer_Standalone example:

 

I'm not sure we are seeing the same thing... This is what the circuit should look like:

attachicon.gif2nd-UART.png

 

There should be a second UART connected to Wishbone slot 5 and then instantiated in the code like this:

HardwareSerial mySerial1(2);  //This finds the second instance of a serial port - in our case connected to wishbone slot 5

rxd and txd are not connected in this circuit. Instead we have the normal behavior for a ZPUino design, the rxd and txd pins are connected through the ext_pins_in and ext_pins_out bus and they are the usual Serial object.

 

To forward all data from the 2nd UART that we connect to Wishbone slot 5 and then to the SUMP logic analyzer we use the following code:

HardwareSerial mySerial1(2);  //This finds the second instance of a serial port - in our case connected to wishbone slot 5void setup() {  // put your setup code here, to run once://  delay(3000);    Serial.begin(115200);  mySerial1.begin(115200); }void loop() {  // put your main code here, to run repeatedly:   if (mySerial1.available()) {   Serial.write(mySerial1.read());   }  if (Serial.available()) {   mySerial1.write(Serial.read());   }  }

Serial is the USB serial port and mySerial1 is the serial port we connect to Wishbone slot 5 and the Logic Analyzer core. 

 

No, we are not seeing the same thing - you might be confusing "Benchy_Sump_LogicAnalyzer_Standalone" and "Benchy_Sump_LogicAnalyzer" examples.

 

In my DesignLab 1.0.7 (and all my posts) the example you mentioned above is called "Benchy_Sump_LogicAnalyzer".

 

The example called "Benchy_Sump_LogicAnalyzer_Standalone" looks like:

post-39148-0-40402300-1454774043_thumb.p

and the sketch reads:

int counter = 0;

void setup() {
  // put your setup code here, to run once:
  Serial1.begin(115200);

}

void loop() {
  // put your main code here, to run repeatedly:
  Serial1.write(counter);
  counter++;
  delay(1);

}

(this is the full code, not abbreviated)

 

Your use case is going to be different, but the code that would run on the AVR chip would be similar. According to the Arduino page the Serial ports should work like this:

 

 

You want to connect the rx and tx of the Sump logic analyzer to the hardware serial port of the AVR chip which is on pins 0 and 1 using a circuit on the FPGA like you have already done. Then you want to forward the input and output from the hardware serial port, Serial1, to the USB serial port which is the first serial port, Serial. You do that with a sketch like like this running on the AVR chip:

void setup() {
// put your setup code here, to run once:
// delay(3000);
Serial.begin(115200);
Serial1.begin(115200);

}

void loop() {
// put your main code here, to run repeatedly:
if (Serial1.available()) {
Serial.write(Serial1.read());
}
if (Serial.available()) {
Serial1.write(Serial.read());
}
}

 

That should then have the output from the Sump Logic analyzer going out through the AVR chips USB port...

 

This is exactly like the Arduino example I was mentioning in a post before, right?

Next I will run a sketch like the Arduino Mega serial example code (very similar to

the Benchy_Sump_LogicAnalyzer sketch) in order to forward the serial data as

mentioned. Will keep you informed...

 

So I am still wondering the questions asked before regarding the "Benchy_Sump_LogicAnalyzer_Standalone" as shown here. (especially the rxd, txd, RXD, TXD markers confuse me ;)

 

Please also see the thread here, we are working on improving the Sump Logic Analyzer as we speak:

http://forum.gadgetfactory.net/index.php?/topic/2539-wishbone-version-of-the-sump-blaze-logic-analyzer/

 

Jack.

 

Good hint thanks! Have to read through this as well. Now I have to sit down and do/test these 2 variants finally... ;))

 

Greetings & all the best

post-39148-0-40402300-1454774043_thumb.p

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Hi Jack, it's been quite some time.

 

Good hint thanks! Have to read through this as well. Now I have to sit down and do/test these 2 variants finally... ;))

 

Today I did the test of the JTAG variant.

 

One of the reasons why I did not report back for such a long time is that somehow the interplay between DesigLab and Xilinx ISE (Project Navigator, v14.7, lin64) got broken:

The edit circuit button in DesignLab does not work anymore for my sketches but for examples (after storing as new sketch of course). Additionaly when I try to open the link

sketchdir://circuit/PSL_Papilio_DUO_LX9.xise
in my library sketch edit_library.ino file it does not work. But if I run ISE from command line (/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/ise) and try to open the file
.../circuit/PSL_Papilio_DUO_LX9.xise

from there, it works for most of them. For some of the .xise files I see a huge bunch of libraries in Design tab opened (not only Papilio_DUO_LX9 and Utility).

So to me it looks like

  • the interplay of DesignLab with ISE has issues
  • may be some files for ISE are corrupt know (but my git repo shows no changes)

Is there a way to reset to "factory settings"?

Back to the important part, the test of LogicAnalyzer (JTAG variant):

As in papilio-prog (ioftdi.h) the USB VENDOR and DEVICE are hard coded, I had first to the adopt ioftdi.h line 37 to reflect correct DEVICE (use lsusb to be sure, it starts with 0403:....) and then recompile it. After that it worked and as I interpret the output connected correctly, the OLS worked but showed only 'zeros'. Looking at papilio-prog console output showed:
[...]
Start Capture
Taking too long, aborting and just sending zeroes.
End Capture
Closing socket

So what am I doing wrong? Why is the capture taking too long? (I think I tried it w/o trigger as well)
 

Greetings

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