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Beginner's question DesignLab and ISim simulation

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Hi,

 

I'm workingt on getting started with the DesignLab and ISE workflow, and for that I'm trying to build a simple project without ZPUino.

 

I created a new DesignLab project, edited the circuit in ISE, deleted the ZPUino and everything else from the schematic. I then built a minimal circuit with a clk_divider_30to1hz symbol from the Papilio libraries.

 

I can create a bit file, upload it to the Papilio DUO, and after connecting two LEDs to the configured pins I have two LEDs flashing at 1 Hz and 8 Hz as expected.

 

As a next step I'm trying to run the circuit in the ISim simulator, and I haven't been able to make that work yet. I created a new VHDL test bench, and I added a process for the CLK signal. When I'm starting the simulation, the following warnings appear when the simulation is built:

WARNING:HDLCompiler:89 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68: <clk_divider_30to1hz> remains a black-box since it has no binding entity.WARNING:Simulator:648 - "C:/Users/stm/Documents/DesignLab/divider/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 68. Instance clk_divider_30to1hz is unbound
 
In the wave window the two outputs from the clk_divider_30to1hz symbol appear with an "U" in the "Value" column (see attached screen shot). If I understand it correctly, this means that the two outputs are uninitialzed.
 
Is there any additional configuration necessary in order to run a ISim simulation for a DesignLab project that uses symbols from the Papilio libraries?
 
My test project is also available via DropBox if someone is interested:
 
 
Thanks
Stephan

post-38585-0-49402100-1427660025_thumb.p

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Hello Stephan,

 

The clk_divider_30to1hz vhd file is in the "DesignLab" library so your testbench code is not finding it. Just add the following to your testbench:

LIBRARY DesignLab;USE DesignLab.ALL;

You probably need to close ISE and open it again and then it worked for me. I had to simulate for a couple seconds to see the changes.

 

The other option is to move clk_divider_30to1hz to the "work" library.

 

Jack.

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Hello Jack,

 

Hello Stephan,

 

The clk_divider_30to1hz vhd file is in the "DesignLab" library so your testbench code is not finding it. Just add the following to your testbench:

LIBRARY DesignLab;USE DesignLab.ALL;

You probably need to close ISE and open it again and then it worked for me. I had to simulate for a couple seconds to see the changes.

 

The other option is to move clk_divider_30to1hz to the "work" library.

 

Jack.

 

thanks for looking at my project. Adding the above two lines to the testbench alone didn't help, even after a restart of ISE, I had to move clk_divider_30to1hz to the "work" library, then it worked. Not sure what that means, I will try to read the documentation of ISE about libraries.

 

What I noticed is that the syntax coloring in the editor for the testbench file does display the "DesignLab" name in black, whereas the "ieee" and "UNISIM" library names appear in pink:

 

post-38585-0-07136500-1427734275.png

 

This looks like the vhdl compiler doesn't know about the DesignLab library when parsing the testbench code.

 

Best  regards

Stephan

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hmmm, I started testing by moving to the work library so maybe I never got it moved back properly to the DesignLab library when it worked for me..

 

I'll try to get this sorted out in a future release.

 

Jack

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