Jack Gassett

DesignLab 1.0.4 Released!

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Hi Alvie - sorry I dropped off a bit there. I need high speed because I'm generating pulses through a DAC (so I can vary the amplitude also). I'm using this board to drive an ASIC for testing purposes. 

 

I actually did realize I should go ahead and build an FPGA block in VHDL so I'm working on that. 

 

Thank you for the detailed explanation, it is very useful for my understanding of the reason for delays. Also the variability of cache hits/misses explains the jitter I was seeing.

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