OzieGamma

N-Core CPU

Recommended Posts

Hi,

 

As I don't have my Papili DUO yet (ordered it today), I was wondering: how much of the % of the FPA is used by 1 ZPUino core ?

 

I hope to fit at least 2 cores in the FPGA ...

 

Thanks,

 

OzieGamma

Share this post


Link to post
Share on other sites

Hah, forget about ZPUino multi-core... at least in common multi-core sense. It's a long road (if even possible) to get there, due to several reasons:

 

a ) Due to performance issues, the current ZPUino (extreme core) needs a dedicated stack. So all cores will never actually see the same memory, so they cannot behave as SMP.

b ) You need a proper interrupt router, and a proper reset controller, as well as software support.

c ) There are no memory barriers, nor atomic operations. And no bus-locking mechanism.

 

XTC (XThunderCore) will support SMP, but it's currently under development. It's bigger than ZPU (almost 2x size with medium support like traps, single clock shifter, user/supervisor mode and other modern things [MMU is not ready yet, nor dcache]), but will surely fit nicely on a S6LX25 or larger.

Share this post


Link to post
Share on other sites

Thanks for the answers !

 

I was planning on using my own CPU (I don't care about performance, my challenge is to write a small kernel for multi-core CPUs). And was planning to use hardware message passing which shouldn't take to much space. (About 2 queues * 32 bits/word * 128 words/queue = 1KB of RAM + some logic for interrupts).

 

OzieGamma

Share this post


Link to post
Share on other sites

It seems possible to get a usable CPU down to a bit below 10% of this FPGA.  There's a 442-LUT version of ZPU, for example.  (My own CPU in progress is 549 LUTs at last count -- just a hair under 10%, but it's 16 bit, and incomplete.)  ZPUino's size includes a higher-performance implementation of ZPU, plus various peripherals.  You won't need the performance, and you won't need to duplicate the peripherals for each CPU core, and that should save you some space.

 

OTOH, one can always be surprised by how much space things take up.

Share this post


Link to post
Share on other sites

What usually takes more space are multiplexers (and incomplete 2^N muxers). And they are so easily declared, that most people forget about that fact.

 

On the other aspect, if you're doing a multi-core, you are surely doing it for performance, so no much sense in using the smaller ZPU, because none of the optional instructions are in HDL (are emulated in firmware).

Share this post


Link to post
Share on other sites

I am designing my CPU to run on FPGAs (trying to avoid muxes).

 

Nop I don't care about performance, it's all about Learning how one would build and program a multi-core CPU ;)

Share this post


Link to post
Share on other sites

Most of a multi-core CPU is the memory interface. At least you've got dual ported RAM (with the odd fun 'feature' - definitely read the chip documentation!) so some of the horrible bits are done for you.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now