bithead

USB Issue on AVR side.

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I'm trying to program the AVR side of my Duo.  I cannot do so.

 

I've got Ubuntu running under Parallels on a MacBook Pro, and I've been running ISE (as well as PlanAhead and Vivado) under this successfully.

 

I can successfully load bit files to the FPGA side of the Duo.

 

However, I cannot seem to get DesignLab to even acknowledge that I have a duo hooked up, when I hook up the AVR side.

 

Relevant information:

 

ddb@xilinx DesignLab-1.0.1 $ lsusb

Bus 001 Device 002: ID 203a:fff9  
Bus 002 Device 005: ID 1d50:60a5 OpenMoko, Inc. 
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
ddb@xilinx DesignLab-1.0.1 $ uname -a
Linux xilinx 3.11.0-26-generic #45-Ubuntu SMP Tue Jul 15 04:02:06 UTC 2014 x86_64 x86_64 x86_64 GNU/Linux
ddb@xilinx DesignLab-1.0.1 $ 
 
The "Serial Port" menu is greyed out.
 
To contrast, here's lsusb when I plug in the FPGA side:
 
ddb@xilinx DesignLab-1.0.1 $ lsusb
Bus 001 Device 002: ID 203a:fff9  
Bus 001 Device 005: ID 0403:7bc0 Future Technology Devices International, Ltd 
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
ddb@xilinx DesignLab-1.0.1 $ 
 
So you can see that things make sense on the FPGA side.  And why would the board identify as OpenMoko?

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Looks like it's not in there yet.

Could just add it yourself.

 

1d50 OpenMoko, Inc.   5119 GTA01/GTA02 U-Boot Bootloader   602b FPGALink   6053 Darkgame Controller

 

add

 

60a4 Papilio Duo (AVR)60a5 Papilio Duo (FPGA)

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It's not a matter of the name, that was just a brief comment -- What I'm trying to do is get DesignLab to program the AVR side of things, and no matter what I try it just fails and goes back to the already-loaded "blink pin 13" demo code.

 

I'll try running it on the Windows VM tonight, just to make sure that the hardware side of things is okay, but I prefer getting it to work on the Linux side of things, because the Windows VM is too damn big to keep on my drive.

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Hello bithead,

 

It should just work under linux, it does show up as an OpenMoko device because they were kind enough to provide the VID/PIDs that the DUO is using. But the class of the device is the same as the Leonardo so it should work without doing anything special. Which linux distro are you using?

 

Also, please make sure SW1 is in the up position.

 

Thanks,

Jack.

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I've tried under Win7, and I see the same symptoms. Programming the FPGA goes smoothly, but when trying to program the AVR, it acts as if it cannot detect the board.

 

There are actually some moments where it looks like it thinks it has programmed the AVR, but when the dust clears, it's still just blinking the LED on pin 13, in the same maddening rate.

 

SW1 is at the top. And to be sure that it wasn't a matter of orientation, I tried it both ways.

 

I'm afraid I may have a bum board. Is there anything else I can try to be sure?

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Hello bithead,

 

I would try to restore the bootloader like in this tutorial:

http://gadgetfactory.net/learn/2015/01/15/designlab-quickstart-duo-avr/#Restore_Bootloader

 

You can also try  to run through the test plan:

http://www.gadgetfactory.net/opmanuals/index.php?n=Main.PapilioDUO

 

If no luck with those we will get you a replacement right away.

 

Thanks,

Jack.

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I do not have anywhere near the equipment I would need for the test plan.

 

However, I do see some interesting behavior when I tried burning the boot loader.

 

Under Windows 7, with the device manager window open:

 

I see two com ports, Papilio DUO AVR Serial Port (COM15) and Papilio DUO FPGA Serial Port (COM16)

 

I then execute the Tools->Burn Bootloader... command, with the serial port set to COM16.

 

Burning the boot loader executes successfully. In the device manager, COM15 has disappeared, and "Papilio DUO AVR Bootloader (COM17)" appears.

 

If I then set the serial port to COM17, and load an Arduino sketch, the sketch will execute. But now in device manager, COM17 has gone away, and COM15 (Papilio DUO AVR Serial Port) has come back, and that port has never worked for programming sketches.

 

In order to load another sketch, I would have to re-burn the bootloader and wait for COM17 to reappear.

 

Is this expected behavior? Perhaps I read the tutorials too quickly.

 

 

...having rewatched the tutorial, I see that the switching between AVR Bootloader and AVR Serial Port is expected behavior.  And what I'm seeing is that I cannot load a sketch using the serial port provided by AVR Serial Port. I have to wipe out the sketch by rewriting the bootloader and addressing the AVR Bootloader port directly.

 

I could offer up a few uninformed hypotheses of why this is happening, but I'll pass. Is there anything else I should test?

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Just to rule one thing out for you: I am successfully using a DUO on a Mac with Windows under Parallels. I did have some strange issue at first where I too could not get files to stick, but it cleared itself, and I cannot readily remember what I did. 

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I appreciate the help.  After watching the serial ports slowly go away over time, using Windows 7, I asked for a replacement board.

 

Let me just state publicly that Gadget Factory, and Jack especially, have been wonderful to work with and helpful in any way they can be.  I've been playing with the Papilio platform for a while, starting with a Papilio One 250 and gradually exploring the entire product line.

 

This was a small hiccup, but nothing that would prevent me from ordering one of whatever Jack's next idea is.

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Hi Jack,

 

Sorry to reopen this thread but I also have issues with AVR side of my Papilio Duo.

I`m using Kububtu 14,04 LTS and try to follow the tutorial for AVR side but the upload to the board fails.

The serial port of AVR is /dev/ttyACM0 for me.

When I select it and ask for Upload I obtain the following ( in DesignLab preferences verbosity checkbox are checked for both Compilation and Upload )

/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-objcopy -O ihex -R .eeprom /tmp/build8484831947675701476.tmp/tutu.cpp.elf /tmp/build8484831947675701476.tmp/tutu.cpp.hex Executing  /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-size -A /tmp/build8484831947675701476.tmp/tutu.cpp.hexBinary sketch size: 4,830 bytes (of a 28,672 byte maximum) - 16% usedForcing reset using 1200bps open/close on port /dev/ttyACM0PORTS {/dev/ttyACM0, /dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}processing.app.debug.RunnerException: Couldn't find a Board on the selected port. Check that you have the correct port selected.  If it is correct, try pressing the board's reset button after initiating the upload.        at processing.app.debug.BasicUploader.waitForUploadPort(BasicUploader.java:266)        at processing.app.debug.BasicUploader.uploadUsingPreferences(BasicUploader.java:97)        at processing.app.Sketch.upload(Sketch.java:1681)        at processing.app.Sketch.exportApplet(Sketch.java:1623)        at processing.app.Sketch.exportApplet(Sketch.java:1595)        at processing.app.Editor$DefaultExportHandler.run(Editor.java:2673)        at java.lang.Thread.run(Thread.java:745)

I also tried to run DesignLab as root to check if there were any differences and I obtain the following :

/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-gcc -Os -Wl,--gc-sections -mmcu=atmega32u4 -o /tmp/build5258795649659095730.tmp/tutu.cpp.elf /tmp/build5258795649659095730.tmp/tutu.cpp.o /tmp/build5258795649659095730.tmp/core.a -L/tmp/build5258795649659095730.tmp -lm /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-objcopy -O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 /tmp/build5258795649659095730.tmp/tutu.cpp.elf /tmp/build5258795649659095730.tmp/tutu.cpp.eep /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-objcopy -O ihex -R .eeprom /tmp/build5258795649659095730.tmp/tutu.cpp.elf /tmp/build5258795649659095730.tmp/tutu.cpp.hex Executing  /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-size -A /tmp/build5258795649659095730.tmp/tutu.cpp.hexBinary sketch size: 4,830 bytes (of a 28,672 byte maximum) - 16% usedForcing reset using 1200bps open/close on port /dev/ttyACM0PORTS {/dev/ttyACM0, /dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyACM0, /dev/ttyS0, } => {/dev/ttyACM0, }Found upload port: /dev/ttyACM0/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude -C/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude.conf -q -q -patmega32u4 -cavr109 -P/dev/ttyACM0 -b57600 -D -Uflash:w:/tmp/build5258795649659095730.tmp/tutu.cpp.hex:i Connecting to programmer: .

Although the result seems to be better the upload never terminate :(

I tried to directly launch the avrdude command in a terminal ( both as root and normal user ) and I obtain the following message :

/media/LaCie/synchronized/Rack/Programmation/fpga$ sudo /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude -C/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude.conf -q -q -patmega32u4 -cavr109 -P/dev/ttyACM0 -b57600 -D -Uflash:w:/tmp/build5258795649659095730.tmp/tutu.cpp.hex:iConnecting to programmer: .Found programmer: Id = "Papilio"; type = l    Software Version = P.a; Hardware Version = p.iavrdude: error: buffered memory access not supported. Maybe it isn'ta butterfly/AVR109 but a AVR910 device?

but I don`t know what to conclude from that :(

 

I also tried to use the AVR programming through FPGA but DesignLab generate the following error message :

/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe -f /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 1: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: MZ%G����%@@%G���%@: not found/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 2: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: Syntax error: ")" unexpected

By looking closer it seems that papilio-prog.exe is the windows Papilio Loader :huh:  which I don`t understand being under Kubuntu and unfortunately I don`t know how to make DesignLab use the Linux version of Papilio Load

 

In desperation I tried the tutorial AVR side part that describe how to restore the booloader but DesignLab generate the same error message than when trying to use FPGA to load the sketch on AVR:

/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe -f /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 1: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: MZ%G����%@@%G���%@: not found/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 2: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: Syntax error: ")" unexpected

I`m completely lost and desperate. I don`t know how to debug that... Any ideas ?

 

For information the load of FPGA circuit works properly, I succeed to migrate one of my VHDL design from Papilio One 500k on Papilio Duo successfully

 

Thnaks by advance for your help

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Hello quicky,

 

I just uploaded DesignLab 1.0.3 which upgrades to Arduino 1.5.8 and has some improvements... Can you download the latest version and give it a try. Also, please make sure that the ftdi_user script completes succesfully, it is meant for ubuntu and there may be some differences with your distro that you will need to work through.

 

Jack.

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Hi Jack,

 

I will try it in few hours. For DesignLab 1.0.1 I had to patch ftdi_user script but due to 64bits instead of 32 bits.The only differences between Kubuntu and Ubutuntu are related to Desktop manager...

The ftdi_user script is related to FPGA serial port only or it should also concern AVR serial port ? because the udev rule files generated by this script contains only USB Vendor and Devices Ids that I observe when pluggin FPGA USB side so I`m not to sure to understand why you mention ftdi_user script for AVR USB issue

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Hi Jack,

 

I just dowload DesignLab 1.0.3 for linux64. I ran ftdi_user script successfully ( with the patches to make it really suitable for 64 bits Ubuntu) but the other points the result is worse compared to DesignLab-1.0.1 !

Now it is no more possible to compile the AVR sketch, there is a java exception ! I copy paste below the result obtained when trying to compile the example Arduno basics Blink :

Sketch uses 4,732 bytes (16%) of program storage space. Maximum is 28,672 bytes.Global variables use 42 bytes (1%) of dynamic memory, leaving 2,518 bytes for local variables. Maximum is 2,560 bytes.java.lang.NumberFormatException: null        at java.lang.Integer.parseInt(Integer.java:454)        at java.lang.Integer.parseInt(Integer.java:527)        at processing.app.Sketch.size(Sketch.java:1721)        at processing.app.Sketch.build(Sketch.java:1604)        at processing.app.Sketch.exportApplet(Sketch.java:1625)        at processing.app.Sketch.exportApplet(Sketch.java:1611)        at processing.app.Editor$DefaultExportHandler.run(Editor.java:2666)        at java.lang.Thread.run(Thread.java:745)

To avoid these java/DesignLab issues and concentrate to upload of firmware to AVR could you indicate me precisely a set of command line to execute outside of DesignLab to try to manually upload the firmware to AVR ?

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Arghhh, it's hard to get everything just right across Windows, Linux32, and Linux64. This error is only showing up under linux but I tested under Windows... Looks like I need to give some love to Linux64 here and make sure all is well. I'm working on a new 1.0.4 release for tomorrow to fix these nagging problems...

 

As far as a command line option, I don't have one at the moment. All of my efforts have been focused on DesignLab IDE. The AVR side is just the Arduino Leonardo with some of the pins and VID/PID changed. So any command line examples that work for the Leonardo should work for DUO.

 

Jack

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Hi,

 

My coworker who has also the Papilio Duo has exactly the same issue when trying to load a firmware on the AVR :(

When searching for avrdude error message on Internet I find a lot of Arduino topics where users had exactly the same issues ( avrdude: error: buffered memory access not supported. Maybe it isn't a butterfly/AVR109 but a AVR910 device? ) but it seems there is no magical solution to solve it..

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To try to advance I retry the solution to program the AVR through FPGA as I cannot program AVR directly.

As DesignLab is calling the papilio-prog.exe which is a Windows executable I replace it by a symbolic link on DesignLab-1.0.1/hardware/tools/papilio/lin64/papilio-prog

and then I try to reprogram through FPGA.

At this time serial Port is /dev/ttyUSB0

it seems the load of bitstream succeed :

Binary sketch size: 4,830 bytes (of a 32,768 byte maximum) - 14% used/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe -f /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x24001093     Desc: XC6SLX9Created from NCD file: top_avr_core_v8.ncd;UserID=0xFFFFFFFFTarget device: 6slx9tqg144Created: 2014/09/08 22:13:31Bitstream length: 2724832 bitsUploading "/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit". DNA is 0xd9fc033c4f083ffe/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude -C/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude.conf -q -q -patmega32u4 -cstk500v1 -P/dev/ttyUSB0 -b57600 -Uflash:w:/tmp/build3775892055425291095.tmp/tutu.cpp.hex:i -Ulock:w:0x2F:m avrdude: ser_open(): can't open device "/dev/ttyUSB0": No such file or directory

but the serial port is no more the same when trying to upload the sketch.

I reuse the avrdude command by replacing the serial port by the new One and now it seems that he sketch upload was successfull

 

In your opinion is it normal that the serialPort change ?

 

The remining issue is now that I no more have a design on my FPGA. Is there a way to restablish it automatically after the load of Arduino sketch ?

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The remining issue is now that I no more have a design on my FPGA. Is there a way to restablish it automatically after the load of Arduino sketch ?

 

I answer to myself. I just reload the Design using papilio-prog and it is fine.

 

I also observe that some time the devttyUSB port doesn`t change between the burn of bootloader and the upload of AVR sketch but I don`t know why...

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Hi Jack,

I still cannot get Design Lab 1.04 to program my papilio duo AVR and FPGA.

The serial monitor can receive the data sent back from the startup example.

I'm using Win7 64 bit Home edition.

All my other Arduino USB boards and Xilinx platform USBII works fine.

 

On the bright side, the board (and Design Lab 1.04) works well with Window XP on my notebook.

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Hello Lak,

 

Do the drivers install ok? Can you look to see if the devices show up in Device Manager? Are you getting any error messages? Any information will help us figure out what is going on.

 

Thanks,
Jack.

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Hi Jack,
 
I did some java update etc.. I can now upload using the upload sketches button to the papduo AVR and papduo FPGA 2meg COM2 and COM1 resp.

The COM drivers are all ok under windows 7 x64.
But I still cannot program the spi chip using load circuit button. It hang there showing burning bit file (this may take a minute) until an exception occurred.

The exception is shown in the attached picture.

 

 

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Hello Lak,

 

If you hare having trouble uploading the picture, just go to "More Reply Options" then attach the image under, "Attach Files". Then you can click on the link to add the image in your post.

 

Jack.

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Sorry, been out of town for work.

Pls see attached file.

 

Looks like papilio_programmer got stuck?

 

I'm using win 7 x64 home edition.post-29548-0-92855400-1426582033_thumb.j

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Lak,

 

Does that error happen every time? Also, what is USB Serial Port (Com3)? That should be there for the Papilio DUO... If it appears along with the Papilio then there is a driver conflict.

 

Jack.

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