Corey Kosak

Homebrew Cray-1A

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Ah! I didn't see that he is using the 1600 Spartan 3E Starter kit board...

 

I'm very surprised it would take that large of a chip though. I wonder if he is using distributed RAM or something and that is what is needing so much FPGA fabric. It would be worth taking a look at the code to see if we could fit it in the spartan 6.

 

Jack.

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I'm pretty rusty with Verilog but it looks like the project is implementing 32KB worth of memory as FPGA registers!

https://code.google.com/p/cray-1x/source/browse/trunk/Verilog/cray1/cray_sys_top.v

 

That would explain why it takes so much space, if we used SRAM instead it should fit in the DUO.

 

Jack.

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We live in exciting times! One issue might be that his project is using a 64-bit-wide data bus. The DUO's SRAM data bus is 8 bits right? Adapting to this cause this DUO-based Cray to run a tad slower.

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You could try wiring up an external SRAM chip to any of the Papilio FPGA boards. Another possibility is grafting on the SDRAM controller to make use of the RAM chip on the Papilio Pro.

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We're talking in context of the Papilio though, the Pro has a Spartan6 LX9.

 

I just looked up the specs and it seems it has more BRAM than I had remembered, 32 blocks of 18Kb which works out to 72kB so that should be enough depending on whether it uses any other RAM or ROM.

 

If it uses that many slices of the LX45 then there's no way it's gonna fit though, unless the high usage is due to using slices instead of BRAM for RAM.

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