Corey Kosak

My DUO arrived today

Recommended Posts

ibullock,

 

You cannot just open the xise file directly... You need to open DesignLab and then click the Edit Circuit icon, DesignLab then takes care of adding all of the libraries to the xise file and opens it for you.

 

Jack.

Share this post


Link to post
Share on other sites

Hi Jack - Thank you (on both counts) - I tried through edit circuit, and it did import.... quite a lot more things. However, I am still getting some errors during synthesis (Saving a new project from Papilio_DUO_Quickstart, or New_ZPUino_SOC seems to give same errors.

 

Parsing VHDL file "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" into library DesignLab
ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 10: Cannot find <zpu_config> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 11: Cannot find <zpuino_config> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 12: Cannot find <zpupkg> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
ERROR:HDLCompiler:104 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 13: Cannot find <zpuinopkg> in library <designlab>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.

 

Seems a bit confusing to me because when you look at the file, it appears to be trying to load from the "work" library, which is where those files are loaded. So, I'm not sure why the error message mentions "designlab." Anyway hopefully just something trivial I am missing... Thanks!

Share this post


Link to post
Share on other sites

Does your sram_ctrl8.vhd have this at the top?

library work;use work.zpu_config.all;use work.zpuino_config.all;use work.zpupkg.all;use work.zpuinopkg.all;

Share this post


Link to post
Share on other sites

Yes, it does have that - I am a bit confused by the error. I did notice there appear to be duplicate versions of certain files in different locations (though I checked the sram_ctrl8.vhd file and I think only 1 version is imported in my ISE project, from libraries\ZPUino_2). My sram_ctrl8.vhd file starts with:

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use ieee.std_logic_unsigned.all;library unisim;use unisim.vcomponents.all;library work;use work.zpu_config.all;use work.zpuino_config.all;use work.zpupkg.all;use work.zpuinopkg.all;entity sram_ctrl8 is

It is also throwing errors such as "ERROR:HDLCompiler:69 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\sram_ctrl8.vhd" Line 54: <std_logic_vector> is not declared." But when I searched for those, I think those usually just result from another error, such as a syntax error, in another part of the file.

 

I have just been running "implement top module" - do I need to do any other steps prior to that?

 

Let me know if there is any other info I can give you to try to diagnose. Thank you!

Share this post


Link to post
Share on other sites

ibullock,

 

It would help to post your xise file. But it sounds like you need to clear up the duplicate versions of the files. Do you have any older versions of DesignLab still installed?

 

Jack.

Share this post


Link to post
Share on other sites

What I meant is that there seem to be duplicate copies of certain files in the DesignLab 1.0.5 directory structure. For example, sram_ctrl8.vhd is present in C:\DesignLab-1.0.5\examples\00.Papilio_Schematic_Library\Libraries\ZPUino_1\PSL_Papilio_DUO_LX9 and also C:\DesignLab-1.0.5\libraries\ZPUino_2 . They appear to be similar but not identical. The imports in each one are a tiny bit different, for example, although both of them include work.zpu_config.all ... work.zpupkg. One of them adds work.wishbonepkg.all, and one of them imports unisim after the zpu .. stuff, the other one imports it before. I'm not sure if this actually has anything to do with the current issue, but I thought I would mention it just in case.

 

Just FYI: I do get this when I first run Xilinx - but I'm not sure it's actually important:

Launching Design Summary/Report Viewer...WARNING:ProjectMgmt:430 - DesignStrategies - Strategy file C:/Xilinx/14.3/ISE_DS/ISE/data/default.xds doesn't exist or is empty, skipping.

(Somewhat odd because my Xilinx directory is D:\Xilinx\14.7 .)

 

I used the uninstaller for DesignLab 1.0.4 and installed 1.0.5. I have removed any remnants of the original 1.0.4 structure so hopefully any old versions are safely removed.

 

I tried to attach the .xise directly but it wouldn't let me. So, I renamed it to a .txt. Please rename back to .xise if you want to take a look. Thank you!

 

PSL_Papilio_DUO_LX9.txt

 

I will do an extra computer restart too to see if it magically fixes anything. Currently still getting the same Cannot find <zpu_config> in library <designlab>... etc errors. Sorry for the trouble when this is probably something pretty obvious - but I guess maybe I won't be the only one to run into this issue either? Thanks!

Share this post


Link to post
Share on other sites

Ok, my best guess here is that you might have modified the xise file for the Template projects because all the ZPUino_1 files are not showing up in your xise file in the right format. They are not associated with a view or the work library in your xise file...

 

At this point I would start over by uninstalling 1.0.5, making sure the directory is deleted, and then reinstalling so the template files are correct.

 

Jack.

Share this post


Link to post
Share on other sites

Hi Jack,

 

I think that's what happened - I didn't think I modified any of those projects at all, but I believe due to Xilinx autosaving the project, and the template projects being unable to find some of those files, it must have somehow modified how those files were set up in the template just from opening the project. Anyway, after reinstall it can get all the way through Generate Programing File with only warnings (which I should go back and check probably), so I think things are on the right track now. Thank you!

 

Question - if you do edit circuit before resaving the .ino in a new location, will that break things? Maybe that's what happened? This time, I saved the .ino somewhere else first, and then hit edit circuit (it prompted me to pick a directory again.) I picked the same directory which gave a very strange error message about an infinite loop or somesuch, but seems to have worked okay? Not too important now, just figured if you know what I did wrong it could help to make future software more user-error-proof if desired.

 

- Ian

Share this post


Link to post
Share on other sites

Great! Glad to hear we are making progress here. :)

 

Don't worry about the warning while Generating the Programming File. Xilinx tools are notorious for spewing out endless warning. I only worry about them if a circuit doesn't work...

 

The best method right now is to click the Edit Circuit icon after you make the new project. That will prompt you to save to a new location and will comment out the #define circuit statement. At that point you are live with your own circuit. I just realized yesterday that if you edit the sketch and then save it will copy the circuit into your folder, but it will not comment out the #define circuit statement which leaves your sketch associated with a library circuit. Not the way we want things to work... So just click on the "Edit Circuit" icon first and save to a new directory. That works as it should.

 

Jack.

Share this post


Link to post
Share on other sites

Thanks again, got it to run with a custom SoC with some counters attached to the Wishbone_to_Registers module just as a test. It's great how easy it is to hook various things to that module. I think it took me most of the time to figure out how the stupid bus taps work and also the REGISTER(IO_SLOT(wishbone_slot),0); syntax.

 

Was confused about how to get a .bmm file to use with Papilio Loader (actually wasn't sure how to export the .hex either but that should be easier to find info on)... does the Loader somehow magically figure everything out from just specifying the single bit file? If I use the loader with just the bitfile specified and then disconnect/reconnect USB, reset the fpga, etc. it seems to have my custom sketch (and SoC) loaded correctly still. Obviously not complaining if that's all I have to do each time, but just curious...

Share this post


Link to post
Share on other sites

Hi Ibullock,

..

My overall goal at the moment is to implement some simple modules on the FPGA for motor control, including a quadrature encoder reader and a small module to do PWM and direction control output to a VNH5019A motor driver (basically just fancy H bridge with some protection stuff). Basically trying to do the fast/low level stuff with dedicated modules on the FPGA, and then use either ZPUino or the MEGA32U4 for higher level control. I do have some experience with FPGAs / Xilinx (mainly with Verilog, haven't used the schematic editor in a long time.) So mostly the obstacle has been figuring out how things are setup for the Papilio specifically.

..

For the quadrature decoder you can have a look at Quadrature_decoder for which I plan to write a tutorial this/next week on learn . You could also have a look at new-designlab-librarie . I use also two VNH5019A , but for the moment with the normal arduino mega connected trough UART to the ZPUno. (if you need the modified Poly VNH5019A library write a reply :) ). For the PWM I had a look at opencores, but just with a glimpse at the libs, I couldn't figure out how to modify one of the available ones to get 20kHz. There is also this topic on the forum request-for-comments-new-pwm-module-for-zpuinopapiliodesignlab :)

Filip.

Share this post


Link to post
Share on other sites

Filip, yes, the new PWM is ready, just awaiting integration (and software libraries).

 

Unfortunately I had no feedback on the approach, which would be excellent so I can match the implementation to your (users) requirements.

 

I'll check with Jack when we can include the new PWM infrastructure.

 

Alvie

Share this post


Link to post
Share on other sites

Hi Filip,

 

That quadrature decoder looks nice from my initial look. I am just starting to learn VHDL (used Verilog before). Basic PWM is fairly simple - some of the modules out there might be something fancier than what is needed.

 

At 96MHz, we would want 4800 clock cycles to be one "cycle" of our PWM signal, in order to get 20kHz. That factor seems a little bit awkward but doable. If we used say a 10 bit counter for our main pwm (1024) states, we could have a prescaling counter which effectively divides the main clock by 5 (i.e. the main pwm counter is enabled to advance only every 5 cycles), which would give us 5120 clock cycles, or 18.75 kHz, which seems pretty good. (see e.g. http://www.fpga4fun.com/PWM_DAC_1.html for the very simple counter type design). I doubt I can hear 18.8 kHz sound at least :).

 

I think you could also just do exactly 4800, but your input would have a more strange range (i.e. 0-4800 ish). I'm not sure if it's too important to hit 20kHz exactly though. The previous version is if you still want the full range to be a power of 2 (e.g. the full range of a 10 bit input bus).

 

I haven't completely thought it through, there may be a much better way to do it. But hope that helps to give you ideas! (see also http://www.fpga4fun.com/PWM_DAC_1.html)

Share this post


Link to post
Share on other sites

Hello,

 

I talked with Mike the other day and he has been super, super busy getting a new product out the door at his new job. He said that he expects for there to be a lull in the next couple weeks and that the eBook will be his priority when that happens. 

 

Hopefully it will all work out and we will see something soon. :)

 

Jack.

Share this post


Link to post
Share on other sites

Hello,

 

I talked with Mike the other day and he has been super, super busy getting a new product out the door at his new job. He said that he expects for there to be a lull in the next couple weeks and that the eBook will be his priority when that happens. 

 

Hopefully it will all work out and we will see something soon. :)

 

Jack.

 

Hi Jack,

 

just to know if there are any news on the updated book  :)

 

Thanks a lot.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now