Corey Kosak

My DUO arrived today

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Mine arrived too. Unfortunately dead on arrival.

 

I just received a new Papilio Duo 2Meg version. I was trying to get the hello world example to work. After I put in the #define circuit zpuino_vanilla and view circuit I get see the same circuit as the video. When I load the circuit I get was seems like the appropriate message that it loaded correctly. The sketch compiles properly but when I do the upload I get this message:

 
Cannot get programmer version, aborting
 
Could not contact ZPUino embedded programmer.
The more common reasons for this are:
 
a) You are not specifying the correct port. The port currently selected is 'COM11'
B) The board FPGA is not programmed with a valid ZPUino bitfile.
c) The board is properly not powered.
 
Please review all of above, if problem persists please contact support.
 
 
I am using windows 7. When I plug in the usb mini to the board I see two com ports in the device manager COM 9 and COM 10. I have selected by board and tried uploading from either of these ports with the same result.
 
Also when I try to use the AVR I (with the user switch up) I can see the Atmel driver in the device manager but the AVR does not show up as one of the COM ports. I also tried a windows xp system with the same result. Unfortunately I don't have a linux system to try in on.
 
I will probably return it
 
Ross Fisher

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Hello Ross,

 

Sorry for the trouble you are having. It is very strange that you are able to program the bit file to the board but not communicate over the Virtual Serial Port... Usually it would be all or nothing, but in this case there is USB communication but just not a specific type of USB communication. It kind of leads me to suspect more of a driver problem then a hardware problem. We can send you a replacement board, but I'm concerned that it might have the exact same problem when it arrives. Are you willing to do some troubleshooting of the drivers? Do you have any other FTDI based devices that have been connected to the computer? I see that you have tried on another computer with the same results... That is strange.

 

If you are willing to troubleshoot I would say let's try these things:

 

1) Download the FTDI Driver uninstall tool and use it to remove any other FTDI drivers from your system. Then reinstall the Papilio drivers:

http://www.ftdichip.com/Support/Utilities/CDMUninstaller_v1.4.zip

 

2) Lets load a bit file that already has ZPUino outputting some text over the serial port. Then see if you can see the output when you connect to the FPGA serial port at 9600. I've attached a Quickstart bit file that you should be able to load to the Papilio DUO by going to Papilio/Papilio Loader in DesignLab. Once it is loaded open the serial terminal in DesignLab and set speed to 9600 (or maybe 115200) and see if you see an Ascii table.

 

Jack.

 

 

QuickStart-zpuino-1.0-PapilioDUO-S6LX9-1.0.bit

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I am not sure I really want to do 1). I have other boards I use on the system that work fine and play well with each other and I would rather not risk breaking things.

I did try 2) the bit file succesfully loaded but I didnt get anything back at either 9600 or 115200.

Should I be getting 2 COM ports when I only plug in  just the mini B cable?

 

I do have an old XP systems that should have any FTDI drivers installed. I will see if that works.

I get the feeling most of the development has been done on Linux which I believe has build in support for FDDI

 

Ross

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Just tried it on an older XP system with no prior FTDI drivers--exactly the same error message. 

 

I think either there is a problem with the way your windows installer is working, not to mention how Windows complains about installing drivers without a Windows certification or its a hardware problem on the board. Also, I don't know whether this is relevant but in the DesignLab 1.0.4 preference it lists the Linux ISE location:

I would assume that if I could ever just get past getting an LED to Blink and Hello World being sent over a serial connection, I might have issues when I got to trying to use projects that invoke Xilinx ISE. 

 

If I had a linux box to use I might be able test the hardware in a different software environment, but alas I do not have one. I could send you the board to test under Windows (and also test the installation of DesignLab from the web following the exact instructions you give in the video), unless there are other things I can try that don't involve uninstalling other things on my system.

Ross

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Ross, 

 

Aha! I think I know what is going on. You say that you see two COM ports show up when you plug in the mini USB cable for the FPGA? Can you post a screenshot to show what you are seeing? If two COM ports are showing up then that means that the USB EEPROM settings for the FT2232 are not correct. That is also where the VID/PID for the Papilio DUO are stored. It could be that the EEPROM has not been programmed correctly.

 

You can force a reprogramming of the EEPROM by downloading the Papilio test plans from Github and then going to the Papilio_DUO_Verification folder and running Run_Papilio_DUO_TestPlan.bat. That should setup your Papilio DUO as it is at the factory. More details can be found on the test plan page. But don't worry, you don't need any of the extra hardware on that page to run the test plan script and reprogram your Papilio DUO. 

 

We can of course just send you a replacement board if that is what you prefer, but if you run the test plan you might be able to fix the problem and be up and running sooner.

 

Jack.

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Jack, that seems to make a lot more sense to be that it was something on the board to do with the FTDI. I will test this and send you a screen shot of the device manager when I have a chance. I was wondering if it was ever considered to follow the arduino example and go to the Atmel atmega 16U2 or similar chip for usb communications. Seems to work really well for them and a big improvement over the FTDI boards.

 

Ross

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My Papilio DUO arrived today, and I just did follow the steps in the "Hello World" video. It all worked more or less as expected. The only confusing thing was that in the part when the Hello World program is prepared for upload to the AVR, the LED was already blinking by itself, so I was not sure whether the switching to the AVR really was working. But that is probably due to the fact that the AVR already had a blinking sketch preloaded.

 

I think I don't undestand the whole concept of the DesignLab integration with the ISE tools yet. I now learned in the Hello World example that I can load a zpuino into the FPGA, and I can load a sketch into the zpuino just like I could load it into a plain normal Arduino. The connection is established by the "#define circuit zpuino_vanilla" line in the sketch, and the zpuino_vanilla is a pre-built .bit file. But what if my FPGA design doesn't include a zpuino? Will I need DesignLab then at all, or will I work with the ISE tools only?

 

Nevertheless pretty excited!

Stephan

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Hello Stephan,

 

I'm glad the first steps went well. I'm sorry things are still a little bit confusing, I need to make more and better tutorials. I'm just about to take a week spring vacation and when I get back I expect to go full force into tutorials and making the first experience easier.

 

In the case that you want to make an FPGA design without the ZPUino. You will still want to use DesignLab because it makes many things easier to do and allows you to make a circuit with the schematic editor and the DesignLab building blocks. That is also on the agenda after my vacation to provide templates for the different usage scenario's. If you don't want to use ZPUino but just want a straight FPGA circuit then there will be a template to start from.

 

For now, start a new Papilio DesignLab project and just delete all of the ZPUino stuff.

 

Jack.

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Hello Jack,

Hello Stephan,

 

I'm glad the first steps went well. I'm sorry things are still a little bit confusing, I need to make more and better tutorials. I'm just about to take a week spring vacation and when I get back I expect to go full force into tutorials and making the first experience easier.

 

In the case that you want to make an FPGA design without the ZPUino. You will still want to use DesignLab because it makes many things easier to do and allows you to make a circuit with the schematic editor and the DesignLab building blocks. That is also on the agenda after my vacation to provide templates for the different usage scenario's. If you don't want to use ZPUino but just want a straight FPGA circuit then there will be a template to start from.

 

For now, start a new Papilio DesignLab project and just delete all of the ZPUino stuff.

 

Jack.

 

the tutorials are very good already!

 

But if you want to improve the Hello World tutorial, the sketch that is uploaded should cause a different behavior than what the FPGA and the AVR do out of the box. If I remember correctly, the Papilio DUO board started blinking with 1 Hz right when I plugged it in the first time. So a small change to the sketch like blinking at 2 Hz would make it more obvious that the programming actually worked.

 

Have a nice vacation!

Stephan

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Jack,

so I ran the testplan. It did solve the 2 ports problem, now I only see 1. However the sketch still wont upload to the zpuino with the same message as before (see attached)

post-38648-0-28567700-1426931802.png

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Ross,

 

When you loaded the test plan were you able to see any output on the serial ports? It should be outputting the ASCII table...

 

I'm leaving tomorrow morning for a spring vacation so we are going to send you a replacement board before I leave. I think this is the safest thing to do, I don't want to have this left unresolved for the week that I'm gone on vacation. You should be getting an email with the tracking information for a new board.

 

Thanks!

Jack.

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Interestingly no. The led did flash however possibly indicating that a sketch was put on the FPGA. Also the testplan did load the bootloader onto the AVR chip so after running it I was able to put the sketch onto the avr chip and the serial communication did work from the avr. Since I am currently out of town and I took the board with me, there will be some delay before I can return it. Thanks for your help and I hope the new board will just work from the start.

 

Ross

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After trying the Hello World example I now worked through some examples from the "Introducing the Spartan 3E FPGA and VHDL" eBook by Mike Field. I was able to create a .bit file and I was able to upload it from DesignLab or with the Papilio Loader.

 

What I cannot get to work is to load the .bit file into the flash memory so it is made permanent. I tried to do this with the Papilio Loader 2.7, by selecting "SPI Flash" in the "Write to" drop down list. This is the output that I get:

JTAG chainpos: 0 Device IDCODE = 0x24001093	Desc: XC6SLX9Using devlist.txtJTAG chainpos: 0 Device IDCODE = 0x24001093	Desc: XC6SLX9Uploading "C:\DesignLab-1.0.4\tools\Papilio_Loader\programmer\bscan_spi_xc6slx9.bit". DNA is 0xd955a1ac480deffeDone.Programming time 499.2 msProgramming External Flash Memory with "C:\Users\stm\Documents\DesignLab\Count_LEDs\circuit\DUO_LX9\papilio_duo_lx9.bit".Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits).Programming :......OkUsing devlist.txtDone.SPI execution time 21052.8 msUSB transactions: Write 4171 read 4002 retries 0JTAG chainpos: 0 Device IDCODE = 0x24001093	Desc: XC6SLX9Using devlist.txtISC_Done       = 1ISC_Enabled    = 0House Cleaning = 1DONE           = 1

After that the design does not work. When I press the reset button, the previously loaded blinking LED design comes back to life.

 

What am I doing wrong?

 

Thanks

Stephan

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You need to have Erase, Write to SPI flash and Verify enabled when programming the flash memory.  The flash needs to be erased before the write and it's always good practice to verify the programming.

 

Magnus

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You need to have Erase, Write to SPI flash and Verify enabled when programming the flash memory.  The flash needs to be erased before the write and it's always good practice to verify the programming.

 

Magnus

 

Thanks, Magnus, that led me into the right direction. After switching the Papilio Loader to "Expert Mode" I could erase and then load successfully to SPI flash. After power on my own design is now loaded.

 

In the Papilio Loader's  "Simple Mode" this apparently does not work as expected.

 

Best regards

Stephan

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Hello Stephan,

 

Thank you for the heads up, I just created an issue for this and will make a fix.

https://github.com/GadgetFactory/DesignLab/issues/24

 

It actually explains other strange problems people have been having... Looks like it is the root cause for several other problems recently reported in the forums.

 

Jack.

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Hello Jack,

 

Hello Stephan,

 

Thank you for the heads up, I just created an issue for this and will make a fix.

https://github.com/GadgetFactory/DesignLab/issues/24

 

It actually explains other strange problems people have been having... Looks like it is the root cause for several other problems recently reported in the forums.

 

Jack.

 

thanks for looking into this,

 

Another thing that was difficult for me are how the buttons in the Papilio Loader look. On my Windows 7 machine the clicked and non-clicked state is hard to distinguish.

 

I made a quick change in the Papilio Loader Jave GUI and replaced the JToggleButtons with JCheckBoxes. Original GUI and my GUI compared:

 

post-38585-0-07041900-1427738018_thumb.p

 

The check boxes look much clearer to me. Would you consider to merge a pull request for this?

 

Best regards

Stephan

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Stephan,

 

Absolutely, I've hated those buttons since day 1. :) Please send me a merge request on github and I'll include it with 2.8.

 

Jack.

Pull request created: https://github.com/GadgetFactory/Papilio-Loader/pull/12

 

Independently from that the weird thing is that I now can no longer successfully upload a design with the Papilio Loader to the flash, also not with the original one.

 

That's what I'm getting as output in the loader when I switch on the "Erase", "Write To"/"SPI Flash" and "Verify" buttons:

 

JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Using devlist.txtJTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Uploading "C:\DesignLab-1.0.4\tools\Papilio_Loader\programmer\bscan_spi_xc6slx9.bit". DNA is 0xd955a1ac480deffeDone.Programming time 498.0 msErasing External Flash Memory.Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits).Erasing    :.............................OkVerifying  :Using devlist.txt................................................................................................................................PassDone.SPI execution time 60610.7 msUSB transactions: Write 32978 read 32809 retries 0

I don't see the "Programming" step that I can see in the output when I run Load Circuit directly in DesignLab. And after that the default blinking on-board LED design is active again.

 

What does work is using only  "Write To"/"FPGA", and this is very quick.

 
Best regards
Stephan

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Jack,

I just got home and tried the new board. It works perfectly without any troubles. Will ship back the other one tomorrow. Must have something to do with the FTDI chip for all I can tell.

Anyway, thanks for your help with troubleshooting. I will start on some of the other tutorials now that I can make it past hello world. Looks tike this board will be a lot of fun.

 

Ross

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So, this seems like an okay place to post some new user questions? Here goes:

 

My overall goal at the moment is to implement some simple modules on the FPGA for motor control, including a quadrature encoder reader and a small module to do PWM and direction control output to a VNH5019A motor driver (basically just fancy H bridge with some protection stuff). Basically trying to do the fast/low level stuff with dedicated modules on the FPGA, and then use either ZPUino or the MEGA32U4 for higher level control. I do have some experience with FPGAs / Xilinx (mainly with Verilog, haven't used the schematic editor in a long time.) So mostly the obstacle has been figuring out how things are setup for the Papilio specifically. Some questions: 

 

(I am using windows 8.1 x64, Papilio DUO, DesignLab 1.0.4, Xilinx WebPack 14.7)

 

- Some of the stuff I want to implement (e.g. quadrature encoder stuff) should have direct access to fpga pins. I'm slightly confused by how the Papilio_DUO_Pinout block is setup in the schematics. For example, if I want to wire for example pins Arduino 53 through Arduino 39 (odd) to my own module, should i just sever the current connection to these pins from the "Papilio DUO Pinout" block, connect them to my own block instead, and then connect my own block e.g. to one of the wishbone bus slots somehow? It seems this should work, but I don't really know if it is the "correct" way to do it or more of a hack.

- When I try to open a Xilinx project made from Papilio_DUO_Quickstart, it seems to be missing ZPUino_1 files. Is there a way to get these files? I see ZPUino_2 FPGA stuff in my libraries folder, but not ZPUino_1.

- Is there a standard way set up to transfer data between the hardware AVR and ZPUino? I see some AVR_Wishbone bridge type thing referred to here and there, but when looking at the 1 or 2 example projects that seem to relate to this, it is hard for me to even figure out what processor the code is supposed to be uploaded to. Is this a work in progress or something that works already / has been used?

- I was slightly surprised to see the separate oscillator for the AVR and FPGA as it seems it could make data transfer between the two more difficult, but I don't know too much about the tradeoffs/requirements in implementing these things. Are there any nice ways to sync up a clock in the FPGA with the AVR? Just seems it might help in reducing the complexity of data transfer, e.g. you could possibly just read/write bits directly across sometimes without having to use synchronizers/FIFO/etc. Anyway, mostly just curious if there is an easy solution, such as outputting the clock from the AVR on some pin, which is then used to setup a synchronized clock in the FPGA.

- Any nice example code in general I should be looking at to better understand how to accomplish some of these things?

 

Sorry if that is a bunch of questions at once but hopefully mostly not too difficult to answer. Thank you!

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Hello, let me try to answer some of your questions:

 

 

 

- Some of the stuff I want to implement (e.g. quadrature encoder stuff) should have direct access to fpga pins. I'm slightly confused by how the Papilio_DUO_Pinout block is setup in the schematics. For example, if I want to wire for example pins Arduino 53 through Arduino 39 (odd) to my own module, should i just sever the current connection to these pins from the "Papilio DUO Pinout" block, connect them to my own block instead, and then connect my own block e.g. to one of the wishbone bus slots somehow? It seems this should work, but I don't really know if it is the "correct" way to do it or more of a hack.

 

Yes, remove the IO markers from tha Papilio_DUO_Pinout and use them directly on your custom chip if you want. 

 

 

 

- When I try to open a Xilinx project made from Papilio_DUO_Quickstart, it seems to be missing ZPUino_1 files. Is there a way to get these files? I see ZPUino_2 FPGA stuff in my libraries folder, but not ZPUino_1.

 

What version of DesignLab are you using? The latest version is 1.0.5 which is fully migrated to ZPUino_2, ZPUino_1 is no longer supported. You might need to uninstall older versions of DesignLab if it is pulling the wrong thing.

 

 

 

- Is there a standard way set up to transfer data between the hardware AVR and ZPUino? I see some AVR_Wishbone bridge type thing referred to here and there, but when looking at the 1 or 2 example projects that seem to relate to this, it is hard for me to even figure out what processor the code is supposed to be uploaded to. Is this a work in progress or something that works already / has been used?

 

The Wishbone bridge is going to be the way to make this happen. It uses SPI to communicate between the AVR and the ZPUino. This is a work in progress, we still need to make a good demo showing how to transfer data from the AVR to ZPUino.

 

 

 

- I was slightly surprised to see the separate oscillator for the AVR and FPGA as it seems it could make data transfer between the two more difficult, but I don't know too much about the tradeoffs/requirements in implementing these things. Are there any nice ways to sync up a clock in the FPGA with the AVR? Just seems it might help in reducing the complexity of data transfer, e.g. you could possibly just read/write bits directly across sometimes without having to use synchronizers/FIFO/etc. Anyway, mostly just curious if there is an easy solution, such as outputting the clock from the AVR on some pin, which is then used to setup a synchronized clock in the FPGA.

 

No way around doing this, the circuits would not have worked without having their own clock source. To communicate between the chips you will want to use a protocol such as SPI, UART, or just putting data on the IO pins. We don't have good examples of this yet, but will try to get some done soon.

 

Jack.

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Hi Jack - Thanks for those answers so far. I have upgraded to DesignLab 1.0.5 now (Win 8.1 x64) but am still getting missing file errors when I open PSL_Papilio_DUO_LX9.xise in a "save-as" version of the ZPUino_Vanilla circuit

 

WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuinopkg.vhd is missing.
WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuino_config.vhd is missing.
WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpupkg.vhd is missing.
WARNING:ProjectMgmt - File C:/imb23repos/fpga/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpu_config.vhd is missing.
WARNING:ProjectMgmt - File C:/imb23repos/DesignLab/build/windows/work/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/papilio_duo.ucf is missing.
WARNING:ProjectMgmt - File C:/imb23repos/DesignLab/build/windows/work/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/Utility.sch is missing.

 

When I open the schematic I also get

 

ERROR: Could not find symbol "Wing_GPIO"

ERROR: Could not find symbol "Papilio_DUO_Wing_Pinout"

ERROR: Could not find symbol "ZPUino_Papilio_DUO_V2"

 

I am assuming I just need to add some extra library path somehow for the latter issues. Is there a reference already somewhere on how to set this up?

 

Thanks!

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Okay, managed to fix most of those by adding various files to the project, but still stuck on an error:

 

WARNING:HDLCompiler:89 - "C:\DesignLab-1.0.5\libraries\ZPUino_2\ZPUino_Papilio_DUO_V2.vhd" Line 176: <zpuino_papilio_duo_v2_blackbox> remains a black-box since it has no binding entity.

 

Since I included things haphazardly from different locations, I'm not super confident that the schematic symbols all correspond to the right version of the vhd file - maybe that could be causing problems?

 

I do have ZPUino_Papilio_DUO_V2_blackbox.ngc included which I thought would resolve that but didn't.

 

I did have to add a bunch of files from DesignLab-1.0.5\examples\00.Papilio_Schematic_Library\Libraries\ZPUino_1\PSL_Papilio_DUO_LX9\ - that seems like maybe a bad thing since the directory implies the files should be for ZPUino_1 rather than ZPUino_2.

 

Thanks!

 

P.S. for any of you on Windows 8 64-bit, running 32-bit Xilinx project manager seems to be the way to go to avoid it crashing every time a file dialog box is needed.

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