james1095

Expression has x elements ; expected y?

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I'm attempting to port the code for Black Widow, an Atari vector game to the Papilio Pro.

 

Original page is here:

http://spritesmods.com/?art=bwidow_fpga

 

It was written for the Virtex2 series but I did get it to compile in original form for a large Spartan3. The S3 500k however lacks sufficient BRAM so I'm targeting the S6LX9 on the Pro. I got the RAM taken care of but now I'm getting some errors I've never encountered before and I can't seem to find much about them. Below is each offending line of code and the corresponding error it generates. Can somebody clue me in here?

 

 

 

-- Memory decoding: offsets in address map

avgmem_addr<=c_addr(15 downto 0)-x"002000";
 

Line 237: Expression has 24 elements ; expected 16

 

 

 

 

yvmul0<=conv_std_logic_vector(pole,64)*sxt(yv0,64);

 

Line 71: Expression has 128 elements ; expected 64

 

 

 

 

vec_scale<=(x"ff"-instruction(7 downto 0))&"0000";

 

Line 215: Expression has 12 elements ; expected 1

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I don't know but this might have to do with Xilinx using a different HDL parser for Spartan-3 chips vs. Spartan-6 chips.  I had this problem when porting the Propeller Verilog code to Xilinx parts.

 

See this: http://forums.parallax.com/showthread.php/157004-Propeller-1-running-on-Pipistrello-(Xilinx-Spartan6-LX45)?p=1287878&viewfull=1#post1287878

And this: http://forums.xilinx.com/t5/Synthesis/How-to-enable-the-new-parser-for-XST-in-ISE-12-1/m-p/133272

 

Magnus

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Magnus is right, things that were allowed through in Spartan3 are no longer allowed, its usually simple stuff.

 

I'm attempting to port the code for Black Widow, an Atari vector game to the Papilio Pro.

 

Original page is here:

http://spritesmods.com/?art=bwidow_fpga

 

It was written for the Virtex2 series but I did get it to compile in original form for a large Spartan3. The S3 500k however lacks sufficient BRAM so I'm targeting the S6LX9 on the Pro. I got the RAM taken care of but now I'm getting some errors I've never encountered before and I can't seem to find much about them. Below is each offending line of code and the corresponding error it generates. Can somebody clue me in here?

 

 

 

-- Memory decoding: offsets in address map

avgmem_addr<=c_addr(15 downto 0)-x"002000";
 

Line 237: Expression has 24 elements ; expected 16

 

One of the three things above has 24 elements, you want to check the size of avgmem_addr but it does look like x"002000" is the problem. Try x"2000"

 

 

yvmul0<=conv_std_logic_vector(pole,64)*sxt(yv0,64);

 

Line 71: Expression has 128 elements ; expected 64

 

 

 

vec_scale<=(x"ff"-instruction(7 downto 0))&"0000";

 

Line 215: Expression has 12 elements ; expected 1

 

Check the size of all of the elements above, look at my comment in blue for the first one.

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Ah, that was it, thanks guys. It was like peeling an onion, each time I'd fix one error another complaint about elements would pop up. The errors are gone but hopefully the code still works! I had to rebuild the ROMs with Romgen to use different RAM primitives and now I need to redo the DCM for the clocks. That part should be fairly straightforward, I just ran out of time to work on it before I had to go to my real job. It compiles now however with no clocks the entire design gets optimized out.

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Well I got this to build but it doesn't work. The X and Y DAC outputs have the carrier but are not being modulated. I took a detour and worked on Asteroids Deluxe instead and succeeded in getting that going. When I have a chance I'm going to take another look at Black Widow and determine whether the the 6502 core is running. I suspect I broke the vector generator in my attempts to fix those errors I was getting. I may have to sit down and really study that to figure out how to get it working. If anyone else would like to take a crack at it I can post my code and the original from spritesmods.

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Can somebody fill in a few gaps in my understanding? Take this statement for example:

 

avgmem_addr<=c_addr(15 downto 0)-x"002000"

 

 

avgmem_add and c_addr are both 16 elements. What is the -x"002000" doing? I get that it's subtracting something from the value on c_addr and assigning avgmem_addr to that value but what is x"002000"?

 

This is one is a bit more mysterious:

yvmul0<=conv_std_logic_vector(pole,64)*sxt(yv0,64)

 

What does conv_std_logic_vector do?

 

 

I don't understand why vec_scale<=(x"ff"-instruction(7 downto 0))&"0000" is expecting only one element either. vec_scale is 12 elements, instruction is 8 elements, I get that &"0000" is concatenating 4 bits to make that 12 elements. What is x"ff"?

 

 

I've made a lot of progress over the past couple of months but there are still a few critical aspects of VHDL that I have not quite grasped. Feels like I'm *so* close to another crest in the learning curve but struggling to reach it. I need to wrap my head around what precisely this code is doing and why the new parser doesn't like it.

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I don't do vhdl but from a programmers point of view I would guess -x"002000"

is offsetting c_addr(blah) by 0x2000 (which incidentally is 8192 in decimal.. Or 8k)

vec_scale<=(x"ff"-instruction(7 downto 0))&"0000"

0xFF is 11111111 (again hex conversion to binary)

So 11111111-instruction(7 downto 0)) & 0000 is 12 bits

Edit :: totally missed the - in there. Adjusted

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Can somebody fill in a few gaps in my understanding? Take this statement for example:

 

avgmem_addr<=c_addr(15 downto 0)-x"002000"

 

 

avgmem_add and c_addr are both 16 elements. What is the -x"002000" doing? I get that it's subtracting something from the value on c_addr and assigning avgmem_addr to that value but what is x"002000"?

 

-x"002000" means it is subtracting a hexadecimal number. The x means hex and every two digits is an 8 bit number. So in this case you should only have -x"2000" which is a 16 bit hex number instead of x"002000" which is a 24 bit hex number.

 

This is one is a bit more mysterious:

yvmul0<=conv_std_logic_vector(pole,64)*sxt(yv0,64)

 

What does conv_std_logic_vector do?

 

Here is a reference page: https://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/conv_std_logic_vector.html

It looks like you will want to change the size of the vector by changing the second parameter.

 

 

I don't understand why vec_scale<=(x"ff"-instruction(7 downto 0))&"0000" is expecting only one element either. vec_scale is 12 elements, instruction is 8 elements, I get that &"0000" is concatenating 4 bits to make that 12 elements. What is x"ff"?

 

This is starting with hex "FF" which is an 8 bit hex number, then it is subtracting the bottom 8 elements of instruction from hex "FF". Finally it concats 4 more elements onto it. You know "0000" is binary because it does not have the x before it. If it would have been & x"0000" then you would have ended up with a 24 bit number instead of an 12 bit number.

 

I've made a lot of progress over the past couple of months but there are still a few critical aspects of VHDL that I have not quite grasped. Feels like I'm *so* close to another crest in the learning curve but struggling to reach it. I need to wrap my head around what precisely this code is doing and why the new parser doesn't like it.

 

Hopefully that helps,

Jack.

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That's making a lot more sense now. It's still a mystery to me why line 215 is expecting 1 element when it has 12. Looking at it, I would expect 12 elements, any idea where it's getting one? It's one 8-element vector subtracted from another 8-element vector with 4 more elements tacked on the result, that should be 12 elements. I'm almost positive I checked further up and vec_scale is also 12 elements.

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