andymanone

New ongoing great project on Papilio Duo - complete Implementation of different Classic Computers (e.g. ATARI 8/16Bit, C64, Amiga)

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Hi @all,

 

here I want to start now a bigger topic.

 

with the power of the brandnew generation of Papilio Duo, I got the idea,

to implement some complete classic computers (like Atari XL/XE, Atari ST, ATARI 2600, Commodore C64, Amiga and others) 

inside the Papilio Duo.

So you be able to load Diskimages or Module-Images (Games, Demos and Tools (like Assembler or others) into the FPGA.

Other (than the idea of Retrocade), you´ll got an complete working, full programmable System (instead of only the Soundchips)

 

I´ve discussed this topic also with Jack and he is enthusiastic about the idea)

 

So I´ll start now, with Mark (a friend of mine and a genius :)).

First of all, we´ll start to work on the implementation of an very high compatible ATARI XL/XE core for the Papilio Duo (together with the 

proper Computing shield).

 

Any ideas, additional informations or close planned projects are welcome!

 

So we´ll hope for a lot response and feedback!

 

Thanks,

 

andY

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I'd be more that happy to port the Acorn Atom FPGA implementation to the Duo:

https://github.com/hoglet67/AtomFpga

http://www.stardot.org.uk/forums/viewtopic.php?f=44&t=6313&hilit=atomfpga&start=150#p88030

 

This is currently a DIY wing for a Papilio One (which includes the ZPU core running the SDCard stack)

 

Jack, I wasn't part of the Kick Starter - when are Duo's likely to be available through distributors?

 

Dave

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Dave, 

 

Absolutely, this is the type of thing that the DUO and DesignLab are meant for. It would be great if you could turn your Acorn Atom implementation into a DesignLab library to share with the community. If we start another topic I can assist with the process as time permits.

 

Thanks!

Jack.

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Jack, I wasn't part of the Kick Starter - when are Duo's likely to be available through distributors?

 

Dave

 

Does anyone have any info/updates on the Duo availability for those who missed the Kick Starter round?

 

It's kind of hard to do a port like this without the hardware.

 

Dave

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Firstly apologies for the lack of updates here. I'll be porting my Atari 800XL core to the Papilio Duo. I've not had much (errr ... any!) time to work on it since I received the board on just about the same day my daughter was born. I'm starting to get a bit of time back slowly so hope to start this properly in the next month or two.

The Papilio Duo is an interesting platform, providing a simpler way of using an FPGA from the Arduino. This is kind of backwards for me since I'm pretty familiar with vhdl but have never used an Arduino. So all that side is new to me.

Anyway think I need to watch a few more videos to figure out the flow between all the components. I'd usually find out pinouts then just wire up a vhdl top level and compile with ISE. Here I think I need to create a design lab component. I guess this is some kind of vhdl/verilog wrapper + some metadata. Then I think I can use design lab to wire up the ports and plug the arduino in as a DMA master on which I can run the firmware. Of course it's possible I've misunderstood how this should work:)

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Well I made a start by installing design lab. Not off to a great start yet though, but I did only have 20 minutes. The link for how to create design lab libraries in design lab is broken: http://gadgetfactory.net/learn/2013/10/29/papilio-schematic-library-getting-started/. Also I haven't actually managed to find the visual circuit editor! Clicking on edit circuit just seems to load ISE. Well enough for today.

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Hello foft and welcome to the Papilio community. Congratulations on your baby girl, I just had a baby boy four months ago. :)

 

Regarding how to port your Atari 800XL core to the Papilio DUO. First of all, thank you for doing so, and secondly, its not as complicated as you are thinking. With the Papilio DUO the Arduino side of things is optional, you can stick with a straight VHDL/Verilog project and not do anything with the AVR side of things. So don't worry about plugging the arduino in a DMA master. Just think of using DesignLab as a way to share your core as a schematic based library. We can walk you through the process, and if you want I can send you an invite to a Papilio Developer slack chat room. But in a nutshell:

 

  • Download DesignLab
  • Go to Papilio/New DesignLab Library
  • Make sure the Papilio DUO FPGA board is selected as the board type.
  • Press ctrl-k to open the new libraries directory
  • Copy all of your source code into the new library directory that was created.
  • Click the Edit Circuit icon
  • You should be in Xilinx ISE.
  • You can delete the contents of the schematic file.
  • You should see that your source code is included as a library.
  • You can right click on your top level file and under process find an option to generate a schematic symbol. (You might need to temporarily move the top level file into the work library.)
  • You should then be able to include the newly generated symbol into the top level schematic.
  • Add I/O markers that map to the pins in the existing ucf file.
  • That should be it.

If that doesn't work out then if you want to just make a project without the schematic symbol I can do the rest.

 

Thanks!

Jack.

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Thanks Jack. Congratulations!

 

So to approach this as a pure FPGA VHDL project. I have a source svn which builds for about 6 platforms, some Altera based some Xilinx based. I build this with scripts on Linux. So I need a .ucf file with the pinouts of the board including the computing shield. From that I should be able to get a build running and generate a .bit for programming.  I guess I can program a bit with the jtag (after turning off the ftdi stuff) to get going. I have my project setup with a 'hello world' top level that just needs a clock and VGA output and uses the block ram for rom/ram. So getting the system to appear quickly, albeit without any form of input, is very quick. I'm hoping I can get that far in the next week (20 mins * 3 nights!), after which the rest tends to be fairly easy.

 

From there I'm not sure how this fits into the Papilio ecosystem:) I was thinking that I could create several fpga components and wire them up in the design lab. Much like the schematic editor in Quartus, except perhaps a little simpler. Is the idea that I create some kind of ISE schematic component, wire than up in ISE then generate a PDF view of the circuit for design lab? Then in design lab I write the software.

 

Signed up to slack but I'll leave that for another night - should be sleeping now:)

 

Mark

 

edit: Also is there a standard .ut file for the Papilio? I'm not familar with this file but for e.g. Replay it seems to define a few pins as having pull-ups etc.

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Here is the standard ucf file for the Computing Shield on the Papilio DUO:

http://forum.gadgetfactory.net/index.php?/files/file/238-computing-shield-generic-ucf/

 

For reference, here is a nice pin diagram:

http://papilio.cc/uploads/Papilio/Papilio%20DUO%20pinout%20for%20CC.pdf

 

If you generate a bit file I'm sure there are plenty of people here who would be happy to test it on their board. :)

 

You can load the generated bit file to the Papilio DUO using the Papilio Loader if you are not ready to install DesignLab yet:

http://forum.gadgetfactory.net/index.php?/files/file/10-papilio-loader-gui/

 

For fitting into the Papilio ecosystem. Yes, I think that sounds perfect, if we can break the project down into components that people might be able to use in other projects then that is perfect. But if that is not practical then just having a schematic based version of your project that allows people to do things like change the joystick mapping, or connect a ps/2 keyboard to joysitck converter so they can make the project their own is the goal.

 

As far as the PDF view of the circuit goes, one of the projects that is being worked on right now is a java based viewer for Xilinx sch files so we can integrate it into DesignLab and generate a view of the schematic on the fly. So the PDF view will hopefully not be necessary much longer.

 

Finally, the last piece of the puzzle that we are working on for DesignLab is a modified version of ROMVault which can be used to manage all of the Atari 800XL games, utilities, and software that can be used with your core. Felix has made some great modifications to ROMVault that allows us to use it to not only manage ROMs but also merge the roms into your bit file and load them to the Papilio with a simple click of a button. Felix just released this tool the other day and we should be working on integration with DesignLab soon.

 

Jack

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Firstly apologies for the lack of updates here. I'll be porting my Atari 800XL core to the Papilio Duo. I've not had much (errr ... any!) time to work on it since I received the board on just about the same day my daughter was born. I'm starting to get a bit of time back slowly so hope to start this properly in the next month or two.

The Papilio Duo is an interesting platform, providing a simpler way of using an FPGA from the Arduino. This is kind of backwards for me since I'm pretty familiar with vhdl but have never used an Arduino. So all that side is new to me.

Anyway think I need to watch a few more videos to figure out the flow between all the components. I'd usually find out pinouts then just wire up a vhdl top level and compile with ISE. Here I think I need to create a design lab component. I guess this is some kind of vhdl/verilog wrapper + some metadata. Then I think I can use design lab to wire up the ports and plug the arduino in as a DMA master on which I can run the firmware. Of course it's possible I've misunderstood how this should work:)

 

Hey Mark, 

so great to meet you here!

 

I know, that you don´t have enough time for things like this, thats why I´m very happy , that you back again now :)!

 

 

Looking for next news !

 

 

BR,

andY

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Thanks for the advice Jack.

 

I'm starting with a plain Xilinx fpga project creating a bit and holding the arduino in reset. Next phase can think about splitting this up and making it more papilio like. I've committed the first code that builds to my svn, but don't try it yet! I need to change the PLL settings, then wire up the sram (need 32-bit access in 4 cycles for the ZPU). Close though I think.

 

Its a pretty tight fit in the LX9. There is another LX9 based port of the a8 core (Aeon lite) and that just fits after I disabled stereo and optimised a few odds. Still should run pretty well and turbo mode should be nice and fast with at 10ns SRAM.

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Should add I'm not sure how ROMvault will fit in. Currently the core has disk drive emulation on a ZPU and hardware multi-cart logic. The ZPU loads the cartridge images/disk sectors into RAM.

 

Perhaps I'll have a core version with the ZPU stripped out and as a schematic object, just exposing the interface the ZPU is using for the ROM vault integration.

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Ah, ok, well maybe that will negate the usefullness of ROMVault. The way romvault works is to use the data2mem tool to merge images into BRAM space inside the FPGA.

 

Jack.

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it would however be useful for adding the different discrete system bitfiles into the xml file as a menu item for a 'one click install' to switch the current system loaded into the DUO :)

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I fixed enough that should boot the system, with no inputs. No dice:-(

 

However my hello world example isn't working, so must be something trvial with the build:

LED1 <= '1';
LED2 <= '0';
LED3 <= '1';
LED4 <= '0';
 
hmmmm (edit: ucf not picked up, oops)
 
edit2: boots...  :D

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OK so far we have:

system boots

video works (15khz pal, composite sync on hsync)

audio untested (but should work)

joystick 1 works

joystick 2 untested (but should work)

64k system using sram chip

 

Here is the bit in case anyone wants a try:

http://www.scrameta.net/autobuild/papilioduo.bit

 

It will be more fun when I wire up the zpu, so software can be loaded. Then need to think how to arduino can be used...

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Working builds of the Atari 800XL core here:

http://www.scrameta.net/autobuild/20150328/papilioduo/

 

See the manual linked here -  the SD card needs setting up like the DE1:

http://www.scrameta.net/

 

Some differences from other platforms - 512KB and LX9 is a bit tight:

i) Mono pokey

ii) No turbo freezer

iii) 64KB max for cartridges (32KB of which is shared with directory listings)

iv) 64KB for directory listings, so not too many files/dir on the SD card.

v) Max mem configuration is 320KB (Compy shop or Rambo)

vi) No covox

 

Seems to run reliably for me.

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