Seba

External RAM

Recommended Posts

Hi,

 

I am new to the FPGA and thinking about ordering Papilio One 500K.

I am wondering weather is it possible to connect soft processor (ZPUino) to external ram through papilio I/O pins like for instance DDR memory?

Well I know that papilio doesn't have near enough I/O ports but with shift registers it could be done? Is this in theory possible, even with longer wait time for memory response?

It would be quite fun project :)

Share this post


Link to post
Share on other sites

Possibly? Yes. Practical? No.

The speed of signals needed to operate a SDRAM chip property make this impractical. If you were to run you serial interface at 100MHz, and used ram with a 16 bit data bus the SDRAM chip would be clocked at about 6MHz.

There are however static RAM chips with a serial interface that could be used, that require only three or four wires.

Share this post


Link to post
Share on other sites

Cool, i know there would be quite alot of perfomance dropdown on the processor but I don't quite care that much about that.

It would be cool to have arduino-like platform with GBs of RAM  :D maybe to slowly run emulators  :P

 

Anyway, thank you for your quick response!

Share this post


Link to post
Share on other sites

Yes, I am familiar with those SRAM chips, infact I already used them on arduino few years ago (but 32KB ones) but here I'm just wondering what would it take to actually get DDR/2 socket module, some bunch of shift registers and plugging actual ram for desktop which contains storage in GBs. I know it would be pretty difficult since those ram modules have their minimum speed limit but maybe by having a seperate core in FPGA that takes care of RAM calls it might reach those limits? 

I know that what I'm asking would be very impractical and who knows weather I'll actually make it work but I like doing that kind of projects that seem very pointless  :rolleyes:

Share this post


Link to post
Share on other sites

I actually did something along these lines once using a CPLD. 

http://papilio.cc/index.php?n=Papilio.CRAMWing

 

In the case of the CRAM Wing I wanted to use it to add more memory to the Logic Sniffer. Since the Logic Sniffer always just counted the memory address up or down it was possible to eliminate all of the address lines and just have data that was incremented or decremented. It worked perfectly but I never actually released it as a product.

 

I had also thought about schemes where you send the address you want in one cycle and then read back or write the data in the next cycle.

 

Jack.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now