hib1

Binary up counter - VHDL example code needed

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In the FPGA book “Introducing the Spartan 3E FPGA and VHDL” by Hamster the Project 10.7, Binary up counter, does not give any VHDL code. It says “Using the above template, extend the project to use a 30-bit counter ("29 downto 0"), displaying the top 8 bits on the LEDs”. Does anyone have VHDL code for this or a similar counter that will display data on LEDs on the Logic Start board or on pins of the Papilio One?

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Hi Hib,

 

If you email me (hamster at snap dot net dot nz) and I'll send you back the source. I have been busy at home lately, and an email will jog my memory!

 

Mike

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I've made it back to my laptop and my memory hasn't failed me...

 

I've only got the design that it is building up to to hand, but this should give you the idea,

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;  entity counter30 is    Port ( clk : in  STD_LOGIC;           enable : in  STD_LOGIC;           count : out  STD_LOGIC_VECTOR (29 downto 0));end counter30; architecture Behavioral of counter30 is   signal counter : std_logic_vector(29 downto 0);begin   ------------------------------------------------------------------------------------------   -- You would assign you LEDs here if this was in your top level module.   ------------------------------------------------------------------------------------------   count <= counter;  count_proc: process(clk)   begin      if rising_edge(clk) and enable = '1' then        counter <= counter + 1;     end if;  end process; end Behavioral;

And here is the top level for using two counters in the one design:

 

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Switches_LEDs is   Port ( clk : in std_logic;         switches : in   STD_LOGIC_VECTOR(7 downto 0);         LEDs     : out  STD_LOGIC_VECTOR(7 downto 0)); end Switches_LEDs; architecture Behavioral of Switches_LEDs is   COMPONENT counter30      PORT(      clk : IN std_logic;      enable : IN std_logic;                count : OUT std_logic_vector(29 downto 0)      );   END COMPONENT;    signal count1 : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');   signal count2 : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');begin   LEDs(3 downto 0) <= count1(29 downto 26);   LEDs(7 downto 4) <= count2(29 downto 26); counter1: counter30 PORT MAP(   clk => clk,   enable => switches(0),   count => count1); counter2: counter30 PORT MAP(   clk => clk,   enable => switches(1),   count => count2);end Behavioral;

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Mike,

 

I am getting the following error messages for the top level for using two counters in one design. Please suggest a solution.

ERROR:NgdBuild:604 - logical block 'counter1' with type 'counter30' could not be

resolved. A pin name misspelling can cause this, a missing edif or ngc file,

case mismatch between the block name and the edif or ngc file name, or the

misspelling of a type name. Symbol 'counter30' is not supported in target

'spartan3e'.

ERROR:NgdBuild:604 - logical block 'counter2' with type 'counter30' could not be

resolved. A pin name misspelling can cause this, a missing edif or ngc file,

case mismatch between the block name and the edif or ngc file name, or the

misspelling of a type name. Symbol 'counter30' is not supported in target

'spartan3e'.

.

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hib1 -- One possible cause of those errors is if "counter30" is missing from your project.  See if the files containing both the pieces of VHDL code from Hamster's post are included in your ISE project.

 

I tried this out just now: copied those two pieces of code into two files, added both files to a new ISE project, and built it.  And it succeeded, without errors and mostly without warnings (what warnings I got may relate to the fact that I didn't bother including a constraint file).  Then I removed the first one, the one which defined counter30(), and tried building again:  It failed with the same two errors you list.

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