Chris_C

Rising_edge and falling_edge

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Allthough I could simulate some code which conditionally checked rising and falling edge, when it synthisised it spewed yet another cyptic error message

 

statement is not synthesizable since it does not hold its value under NOT(clock-edge)

 

I really need an error message to english translator!

 

So I changed my logic about for the input it was complaining about and eliminated the falling edge check

then it complained about the same thing but for a different input

 

should I be using different processes for rising and falling edge, but then whats the best way to "communicate" between processes

 

for example I can't really see how hardware could drive the same signal from two places?

 

Assuming my logic really could only be done by detecting rising AND falling edge whats the best way to go about it...

 

(incidently by changing my logic round I have a working module but I'm interested to learn about this for future pain with ISE)

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Hi Chris,

 

It would probably be helpful to show us the code, but from your description here's my guess.  Xilinx registers and memories can only be clocked with one clock edge.  You can choose rising or falling for each register, but not both.  ISE cannot synthesize logic that requires a register to be clocked with both edges.

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Unfortunately I rewrote the code to work round it but in one process

 

DoPulse process(clk,pulsein)

 

 If rising_edge(clk)

...

If falling_edge(clk)

...

If falling_edge(pulsein)

 

 

 

I can see why it would complain about falling clk but after its removal it complained about falling pulse in

 

Is it possible to drive 2 buffers from say clk and detect rising on the output of one buffer and falling on the other ?

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... I can see why it would complain about falling clk but after its removal it complained about falling pulse in

 

Is it possible to drive 2 buffers from say clk and detect rising on the output of one buffer and falling on the other ?

 

I'd have to see more code to help with why exactly it's complaining.  Plus, I use Verilog so I have limited knowledge of VHDL.

 

For the second question: yes, you can have two buffers, one that detects rising and one that detects falling.  However, the best way to detect edges depends on your application.  For example, when designing an I2C slave you need to detect rising and falling SCL and SDA.  They're probably much slower than your FPGA master clock which is (by default) 32 MHz on a Papilio One.  So one way to detect edges is to sample an input using the 32 MHz clock and compare the latest value sampled "new" to the previous value sampled "old":

 

   rising_edge = new & ~old

   falling_edge = old & ~new

 

It's generally best to have a single clock for all your synchronous logic -- crossing clock domains is nasty.

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My code as it stands now is working!

 

I wanted to get a better understanding of rising / falling generally

 

Add and end process and three endifs and throw something inside the ifs so they don't get optimised out and that should reproduce the error

 

If you are particularly interested I could try to reintroduce the error into some fresh code

 

One thing I find tiresome about the tools.  (One of many things alas) is the fact it would simulate just fine, but not synthesise - what's the point of a simulation that doesn't actually simulate the limitations of the target device !

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One thing I find tiresome about the tools.  (One of many things alas) is the fact it would simulate just fine, but not synthesize - what's the point of a simulation that doesn't actually simulate the limitations of the target device !

 

Both VHDL and Verilog started as simulation languages.  Synthesis -- and particularly synthesis for FPGAs -- was added later.  So it's easy to write code that simulates but is not synthesizable, or synthesizes into a poor implementation.  Simulation and synthesis are done by different companies, so it's pretty hard for the simulation company to know what's actually synthesizable.  Plus, the simulator may target lots of different FPGAs and even non-FPGAs.

 

I have a simple but unconventional approach -- I just don't do FPGA simulation.  I use a development board and/or prototype hardware.  In most of my designs, creating a simulation test bench would be several times harder than designing and debugging the logic, so it would be a poor use of my time.

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@johnbeetem logisim http://www.cburch.com/logisim/ is simple even does rudimentary propagation delay and is fantastic getting the pure logic right!  You can bash together a logic circuit to test you logic is OK in probably less then 10% of the time you could using schematic capture / simulation and its a lot more user friendly!

 

@hamster I'm missing the point as i fail to see how that's better than a counter ? (the pulses must be at least 6 clocks apart?) Perhaps you'd like to make a separate post so others don't miss it?

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@Chris_C: I think the point of the flancter is not the counting (that's just given as an example) but handling input pulses that are so short that you can't sample them with your clock.  I gather that crossing clock domains, or dealing with asynchronous (clockless) data, is quite a pain.  That's what would make the flancter useful.

 

Re synthesis:  I've also heard that what's synthesizable on one FPGA might not be on another; or even with a different synthesis tool.  Another reason I can think of that you might want to simulate something you can't synthesize, is if half your circuit is synthesizable RTL (your circuit in all its glory) and the other half is a non-sythesizable behavioral model.  Like perhaps that second part isn't done yet; or it's something you're going to buy and this is just a sample; or it's an off-FPGA component on your board.

 

Re simulation:  My simulator of choice is Icarus Verilog.  Free, relatively capable, command line oriented.  But so far I seem to be using it more for debugging than testing.  Also a quick (if over-lenient) syntax checker.

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