Xilinx VHDL UART Example

[assafi 0]

Hi everyone!

 

I was trying to implement the UART example from the Papilio website and was dissapointed to find out that the link for the example project from Gadget Factory is broken

Can anyone share this project? currently I cannot enjoy the tutorials...

 

thanks!

[Jack Gassett 0]

Hello Assafi,

 

That server just recently went down, its very old and I thought we had everything migrated off it. Let me dig up that source code and post it to a new location.

 

Jack.

[Jack Gassett 0]

Ok, I found the code and am attaching it to this post, I'll update the original article too.

 

Xilinx_UART_Example-1.1.zip

 

Jack.

[assafi 0]

Thanks!

[tdoodnauth 0]

Thanks as well. 

[Jack Gassett 0]

Look for this to be implemented soon in DesignLab, I figured out how to use a netlist file so we should be able to distribute a working version that doesn't require downloading the source code without violating Xilinx's EULA's.

 

Jack.

[ruzzmon 0]

Hey Jack,

 

Any chance you were able to implement this idea already into DesignLab? I couldn't seem to find it. I was looking for an easy way (drop-in) to communicate with some registers on the FPGA without the ZPUino/other soft processors. Any other suggestions to do this would be useful as well.

 

In fact, it'd be really cool if there was something like a UART that could talk to the wishbone bus registers directly. Is that possible? That would mean we could reuse all the work that people may put into developing wishbone compatible peripherals but who may not need the power/functionality of the ZPUino.

 

Thanks

[Jaxartes 7]

There's something called "UART to bus" at open cores.  I think it provides basically the functionality you're looking for, except it's not wishbone compatible and it's not DesignLab integrated. 

 

http://opencores.org/project,uart2bus

 

There are probably others out there.

[Jack Gassett 0]

That is an idea I've been kicking around for a while now, just haven't had the time to implement anything... Maybe that opencores project is a good fit.

 

Jack.

[ruzzmon 0]

Hi guys,

 

That opencores project Jaxartes posted seems like a perfect fit! 

 

In the future this means we could generate hardware peripherals for DesignLab library that could be instantiated as either standalone or ZPUino-connected which I think is pretty neat and adds some flexibility and reusability.

 

Thanks

[Jack Gassett 0]

The only downside is that it is not Wishbone compatible, but might be easy to adapt to Wishbone.

[ruzzmon 0]

Is anybody working on this or interested in working on this? I doubt I'd have the knowledge and skill at this point to do it myself...

 

Thanks

[Jack Gassett 0]

Unfortunately I don't have much time available to work on it at the moment... But I'm all for it and will offer a $100 Gadget Factory credit to anyone who can make this a reality!

Jack.

[ewill 0]

The Uart example is very close to what I'm after for communicating with an external device I have.

 

http://papilio.cc/index.php?n=Papilio.HighSpeedUART

 

However I need an 11 bit frame of data and the example uses a 10 bit frame. Is there anyway the code can be modified to allow for 2 start bits and 8 data bits or 1 start bit and 9 data bits? I always need 1 stop bit regardless.

 

I'm new to FPGAs and have poked around in the code but need a little direction to get me started. 

 

Thanks.

[ewill 0]

OK 9 bit example is also included with Xilinx code package. Thanks.