hamster Posted October 4, 2014 Report Share Posted October 4, 2014 I've got fed up with how long Coregen takes to make a small single-clock-domain FIFO, so have written two different ones from scratch. http://hamsterworks.co.nz/mediawiki/index.php/Inferred_FIFO I found the logic quite tricky to implement from scratch - lots of interesting cases to think about. Link to comment Share on other sites More sharing options...
alvieboy Posted October 4, 2014 Report Share Posted October 4, 2014 I wrote a small one too for ZPUino, mostly used in UART. Our designs are pretty much similar, except you use "wr_ptr+1 = rd_ptr" and I use "wraddr=rdaddr-1" https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/fifo.vhd For async clocks, I use opencores async FIFO. It's not perfect, but works OK. Link to comment Share on other sites More sharing options...
offroad Posted October 4, 2014 Report Share Posted October 4, 2014 Heh... one of those "compulsory" exercises If I remember correctly, with only a few rows it can be mapped to LUTs so you end up with one LUT per bit.Not for 11 bits address space, though. Link to comment Share on other sites More sharing options...
hamster Posted October 4, 2014 Author Report Share Posted October 4, 2014 Yeah, unless you use the LUTs as a 16 bit shift register, With the output indexed by the read pointer. That way you can store 16 bits per LUT. Link to comment Share on other sites More sharing options...
offroad Posted October 5, 2014 Report Share Posted October 5, 2014 >> 16 bit shift registerbut then the FIFO would have a fixed delay, right? Link to comment Share on other sites More sharing options...
hamster Posted October 5, 2014 Author Report Share Posted October 5, 2014 >> 16 bit shift registerbut then the FIFO would have a fixed delay, right? Nope - the CLB inputs act as "address" registers to a 16 bit shift register, allowing you to select which of the bits to look at. - have a look at http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf "Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs" Link to comment Share on other sites More sharing options...
mkarlsson Posted October 7, 2014 Report Share Posted October 7, 2014 Mike,I noticed you use 4 bit read and write pointers for a 16-entry FIFO. If you use 4-bit read and write pointers to figure out if the FIFO is full (i.e. the FIFO has 16 words stored) then you will get into problem since a 4-bit value can't hold the value 16. Your solution is to say it's full if the FIFO has 15 words stored (wr_ptr+1 = rd_ptr) so you are basically throwing away one location in the FIFO. An alternative way is to use 5-bit read and write pointers. This will allow you to differentiate between empty (wr_ptr = rd_ptr) and full (wr_ptr = rd_ptr + 16). This will also make the logic for detecting full much simpler. In your case you need a 4-bit adder and a 4-bit comparator to detect full (= 15 words in the FIFO) while this method only adds a couple of gates - it's either empty of full if bits 3-0 of wr_ptr and rd_ptr are the same (i.e. your empty detection), the added logic is that it's empty if bit 4 of wr_ptr and rd_ptr are the same, and full if bit 4 of wr_ptr and rd_ptr are not the same. When accessing the memory only bits 3-0 of the read and write pointers are used. Magnus Edit:Looking at your code again I just realized it's a 32-entry FIFO, not a 16-entry FIFO (I wrote the post after reading your code a few days earlier and somehow I remembered it as a 16-entry FIFO). However, the basic idea is still the same, just change "4-bit" to "5-bit" and "5-bit" to "6-bit" etc. Link to comment Share on other sites More sharing options...
offroad Posted October 7, 2014 Report Share Posted October 7, 2014 >> Nope - the CLB inputs act as "address" registers to a 16 bit shift register,Thanks. That is quite efficient. Link to comment Share on other sites More sharing options...
hamster Posted October 7, 2014 Author Report Share Posted October 7, 2014 And Marcus is right (I wouldn't expect anything else! ) The first implementation is one entry shallower than expected. But it just looks so nice that way! I'll have to change the web page to say it is a little shallow. Mike Link to comment Share on other sites More sharing options...
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