ohohnick

Add a new module into ZPUino (Vanilla for Papilio Pro)

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Hi there!

 

I'm trying to add a new mouse module into ZPUino and I followed these steps:

 

(in the ZPUino top level)

 

1. signal part
signal mouse_ps2dz: std_ulogic;
signal mouse_ps2cz: std_ulogic;

2. wishbone part
slot8: zpuino_mouse_test
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(8),
wb_adr_i => slot_address(8),
wb_cyc_i => slot_cyc(8),
wb_stb_i => slot_stb(8),
wb_ack_o => slot_ack(8),
wb_inta_o => slot_interrupt(8),
ps2dz => mouse_ps2dz,
ps2cz => mouse_ps2cz
);

3. pps part
gpio_spp_data(6) <= mouse_ps2dz;
gpio_spp_data(7) <= mouse_ps2cz;
mouse_ps2dz <= gpio_spp_read(1);
mouse_ps2cz <= gpio_spp_read(2);

Because the ps2dz and ps2cz are inout signals

But there is always an error : this line slot8: zpuino_mouse_test is not declared.

I already added the file zpuino_mouse_test into the whole project and I can see it takes the place of "slot 8 empty device"

I don't know why there is an error like this. I will be so grateful if there are some advice. Many thx!

post-37218-0-97268500-1409386205_thumb.p

post-37218-0-75031500-1409386211_thumb.p

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you need to add a declaration (in VHDL) of your module interface before you can instantiate it.

 

If you can copy/paste here the Verilog interface I can do that for you.

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Thx for your reply Alvie. I really lack of knowledge in VHDL...

 

here is the codes of the "zpuino_mouse_test". I just named it with a test but I actually connect the input and output signals of the mouse with the signals of the Wishbone.

 

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
library work;
use work.zpuino_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity zpuino_mouse_test is
 
   port(
   wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
    wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
    wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
    wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
  --  wb_we_i:  in std_logic;
    wb_cyc_i: in std_logic;
    wb_stb_i: in std_logic;
    wb_ack_o: out std_logic;
    wb_inta_o:out std_logic;
 
--zpuino_mouse interface      
      ps2d:  inout std_logic;
      ps2c:  inout std_logic
   );
end zpuino_mouse_test;
 
architecture Behavioral of zpuino_mouse_test is
 
   component mouse is
      port(
         clk:   in    std_logic;
         reset: in    std_logic;
         ps2d:  inout std_logic;
         ps2c:  inout std_logic;
         xm:    out   std_logic_vector(8 downto 0);
         ym:    out   std_logic_vector(8 downto 0);
         btnm:  out   std_logic_vector(2 downto 0);
         m_done_tick: out std_logic
      );
   end component mouse;
 
   signal   xm:    std_logic_vector(8 downto 0);
   signal   ym:    std_logic_vector(8 downto 0);
   signal   btnm:  std_logic_vector(2 downto 0);
   signal   m_done_tick:  std_logic ;
 
begin
 
   m1 : mouse port map(
   clk => wb_clk_i,
   reset => wb_rst_i,
   ps2d => ps2d,
   ps2c => ps2c,
   xm => xm,
   ym => ym,
   btnm => btnm,
   m_done_tick => m_done_tick);
 
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
 
process (wb_clk_i,wb_rst_i,wb_adr_i)
begin
 
if wb_rst_i = '1' then
wb_dat_o <= (others => 'X');
elsif (wb_clk_i'event and wb_clk_i='1') then
case wb_adr_i(2) is
when '0' =>
wb_dat_o(8 downto 0) <= xm;
wb_dat_o(11 downto 9) <= btnm;
wb_dat_o(12) <=m_done_tick;
when '1' =>
wb_dat_o(8 downto 0) <= ym;
wb_dat_o(11 downto 9) <= btnm;
wb_dat_o(12) <=m_done_tick;
when others =>
wb_dat_o <= (others => 'X');
end case;
end if;
end process;
end Behavioral;

 

 

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And here is the Verilog codes for the mouse.v

 

 

`timescale 1ns / 1ps

 
module mouse(
 
    input wire clk, reset,
    inout wire ps2d, ps2c,
    output wire [8:0] xm, ym,
    output wire [2:0] btnm,
    output reg m_done_tick
    );
    
// constant declaration
    localparam STRM=8'hf4; // stream command F4
 
    // symbolic state declaration
    localparam [2:0]
    init1 = 3'b000,
    init2 = 3'b001,
    init3 = 3'b010,
    pack1 = 3'b011,
    pack2 = 3'b100,
    pack3 = 3'b101,
    done  = 3'b110;
 
    // signal declaration
    reg [2:0] state_reg , state_next;
    wire [7:0] rx_data;
    reg wr_ps2;
    wire rx_done_tick , tx_done_tick;
    reg [8:0] x_reg, y_reg, x_next, y_next;
    reg [2:0] btn_reg , btn_next;
 
    // body
    // instantiation
    ps2_rxtx ps2_unit
     (.clk(clk), .reset(reset), .wr_ps2(wr_ps2),
      .din(STRM), .dout(rx_data), .ps2d(ps2d), .ps2c(ps2c),
      .rx_done_tick(rx_done_tick),
      .tx_done_tick(tx_done_tick));
    
// body
    // FSMD state and data registers
     always @ (posedge clk , posedge reset)
     if (reset)
        begin
        state_reg <= init1;
        x_reg <= 0;
        y_reg <= 0;
        btn_reg <= 0;
        end
     else
        begin
        state_reg <= state_next;
        x_reg <= x_next;
        y_reg <= y_next;
        btn_reg <= btn_next;
        end
 
    // FSMD next-state logic
    always @*
    begin
       state_next = state_reg;
       wr_ps2 = 1'b0;
       m_done_tick = 1'b0;
       x_next = x_reg;
       y_next = y_reg;
       btn_next = btn_reg;
       case (state_reg)
         init1:
            begin
              wr_ps2 = 1'b1;
              state_next = init2;
            end
         init2: // wait for send to complete
            if (tx_done_tick)
              state_next = init3;
         init3: // wait for acknowledge packet
            if (rx_done_tick)
              state_next = pack1;
         pack1: // wait for 1st data packet
            if (rx_done_tick)
              begin
                state_next = pack2;
y_next[8] = rx_data[5];
                x_next[8] = rx_data[4];
                btn_next = rx_data[2:0];
              end
         pack2: // wait for 2nd data packet
            if (rx_done_tick)
              begin
                state_next = pack3;
                x_next [7:0] = rx_data;
              end
         pack3: // wait for 3rd data packet
            if (rx_done_tick)
              begin
                state_next = done;
                y_next[7:0] = rx_data;
              end
         done:
              begin
                m_done_tick = 1'b1;
                state_next = pack1;
              end
       endcase
    end
 
    //output
    assign xm = x_reg;
    assign ym = y_reg;
    assign btnm = btn_reg;
 
endmodule

 

 

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You are missing the component declaration in papilio_pro_top.vhd:

component zpuino_mouse_test is  port(    wb_clk_i: in std_logic;    wb_rst_i: in std_logic;    wb_dat_o: out std_logic_vector(15 downto 0);    wb_adr_i: in std_logic_vector(3 downto 0);    wb_cyc_i: in std_logic;    wb_stb_i: in std_logic;    wb_ack_o: out std_logic;    wb_inta_o:out std_logic;    -- zpuino_mouse interface    ps2d:  inout std_logic;    ps2c:  inout std_logic  );end component;

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hi Alvie

 

New errors show up like this. Actually ps2c and ps2d are inout signals and I'm not sure how to connect these inout signals with GPIO.

 

attachicon.gif20140901214732.jpg

attachicon.gif20140901214820.png

attachicon.gif20140901214919.jpg

 

You have two purely combinatorial assignements to gpio_spp_data, and both can't be active at the first time.

 

Just guessing here, but I think you want to delete the first assignment,  the one where "dontCareValue" is assigned

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You cannot attach bi-directional to GPIO, you will have to directly map them into the pins.

 

First, choose where you want to map those pins to (WING_A/B/C). Then, connect them directly to that signal and comment out the GPIO IOPAD instance.

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I will use the PS2 PORT on Arcade MegaWing to connect with the mouse. These two codes are from the ucf file which contains both the papilio pro and arcade megawing.

 

NET ps2d        LOC="P88"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A12
NET ps2c        LOC="P93"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A13
 
how to write these in the ZPUino top file in VHDL? Or I just need to modify the existing ucf file with ZPUino Vanilla for Papilio Pro?

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