Pipistrello OLS now officially supported by sigrok

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The FPGA code is based on the Open Bench Logic Sniffer but using DRAM to buffer the samples instead of the internal BRAM, everything else is pretty much the same including the sample rate (32 channels up to 100 MHz, 24 channels up to 100 MHz, 16 channels up to 200 MHz and 8 channels up to 200 MHz).  I think it should be possible to make a version that does 16 channels up 200 MHz and 8 channels up to 400 MHz but you would need to either hack JaWi's SUMP client or modify the Sigrok driver to support this.



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