Howard1

Documentation for schematics/zap ide

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Is there documentation that answers these questions?

 

How do you edit, load, use schematics with the zap ide?

Are schematics modifiable or can you only plug and play a schematic? 

Can you connect multiple schematics to the fpga and run he at the same time?

Can you program each schematic's behavior as a function of the immediate state of any inputs to the system?

 

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Howard,

 

All of the documentation there is at this point is at http://learn.gadgetfactory.net you can also look at the Xilinx documentation for the schematic editor since everything is built on top of that.

 

This entire project is a large undertaking for me and is going to take some time to pull off. I'm currently working on getting everything in place for manufacturing the Papilio DUO. That is the most time critical component and people underestimate how much work it is... Once everything is on track with manufacturing then I will start up development of the ZAP IDE again, to be called DesignLab, and will get things more polished and documented.

 

 

Is there documentation that answers these questions?

 

How do you edit, load, use schematics with the zap ide?

Are schematics modifiable or can you only plug and play a schematic? 

Can you connect multiple schematics to the fpga and run he at the same time?

Can you program each schematic's behavior as a function of the immediate state of any inputs to the system?

 

For the first question, here is a guide, it might be outdated a bit... 

http://gadgetfactory.net/learn/2013/10/29/papilio-schematic-library-getting-started/

 

All schematics are modifiable, you need to install Xilinx ISE software.

 

Can you connect multiple schematics to the fpga and run he at the same time?

 The examples are not designed that way, but you should be able to modify them any way you want, including running multiple at once.

 

Can you program each schematic's behavior as a function of the immediate state of any inputs to the system?

Anything is possible with an FPGA, whether the examples specifically target this is the question. You would have to explain what you mean a little more...

 

Jack.

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