julien

FPGA in asynchronous mode

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Hi,

 

I may have not dug enough into the Papilo FPGA cards documentation yet, so I am asking here:

 

What about removing the clock? to work in asynchronous mode. How difficult is this with the different cards (I am yet considering buying the Papilio Pro, but answers for the other cards are also welcomed).

 

Does anyone already did it?

 

For information, I am trying to reproduce some results of Dr. David Rosin from Duke University / Technische üniversität Berlin (http://fds.duke.edu/db/aas/Physics/researchers/dpr12), so I really need this asynchronous mode. And I would not go for proprietary devices :)

 

Best,

 

Julien

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Hello Julien,

 

Everything I've learned about FPGA's is that you do not want to remove the clock and work in asynchronous mode... But if you have some advanced scheme that you want to experiment with then there is no reason that the Papilio FPGA would behave any differently from any other Xilinx FPGA board in respect to asynchronous mode.

 

Jack.

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Hi,
 
Thanks for the answers.
 
@hamster: I have already taken a quick look at this project. I have not yet asked any question there...
 
@Jack: I understand why asynchronous mode is usually disregarded. The scheme I want to implement is not that advanced but requires asynchronous mode.
 
By the way, the schemes I am interested in are networks of "autonomous boolean oscillators" (see pictures in http://arxiv.org/pdf/1302.1375.pdf), where one oscillator is usually one inverter gate with time-delay feedback and time-delay feedback is just an even number of inverter gates to just slow the signal.

 

Oscillators are coupled through OR, NAND, XOR or XNOR gates. It has been shown (both by theory and experiments, once again refer to previous link) that these kind of schemes can generate chaotic dynamics, synchronization. But you need asynchronous mode for that...

 

The authors of the paper are wiling to share the code (Verilog), they used a Altera Cyclone IV EP4CE115F29C7N board to implement their schemes. I am planning to implement the same kind of experiments on one of the papilio board. That is why I asked about asynchronous mode :)

 

Best,

 

Julien

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Hi

 

 

You simply either use the flip-flops and clock or you don't, you can use entirely combinational logic if you want.

 

That's exactly what I want to do :)

 

Sorry for not yet knowing the technical language and how all the FPGAs related stuffs. I just seen David's PhD defence 2 or 3 weeks ago, I found all this work really interesting, read the papers (these guys are physicists and may have not used the accurate technical language), planed to buy a card and redo the experiments myself last week, and I am now learning Verilog and lot's of background knowledge about how FPGAs work.

 

So, Is there any specific things to do in the programming stage or compiling stage in order not to use the flip-flops and clock?

 

I may also have to change the title of the topic, no?

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Don't ever use a signal as if it were a clock, and, at least for VHDL don't have any processes that have if's and assign signals in only one branch (this will cause the synthesis to generate storage elements).

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Hi,

 

since you mentioned verilog:

module onetwo(input a, input b, output c);

c = a & b;

endmodule

 

That's pure combinational logic.

 

module onetwo(input a, input b, output reg c, input d);

always @(posedge d) begin

c <= a & b;

end

endmodule

 

And that was synchronous logic, with "d" being a clock pin (you can't really mix the two types of signals, they are physically different on silicon or the design gets rather slow if you do).

 

It's maybe not too useful to think too much about the language. Just learn the patterns.

Note the difference between "=" and "<=" in the 2nd example. Here it doesn't matter, but it's one of the most important things to know.

Sooner or later you'll probably want to implement synchronous test structures for your asynchronous constructs, so don't abandon it immediately as "evil". There's a certain beauty to it, you'll probably appreciate it more after spending some time with purely combinational design :)

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Hi,

 

@offroad:

 

That's the kind of things I wanted to know. Thanks a lot :)

 

Now that I know a little bit more about the vocabulary and its meaning, I can say that the schemes I want to implement are pure combinational logic. I do not reject synchronous designs, I perfectly understand the pros and (the few) cons, I just want to build a small experiment :)

 

Best,

 

Julien

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