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I've been working on a HDMI input wing, and have hit what looks to be a potential major snag. The TMDS input requires 50 ohm termination resistors to 3.3V on the differential inputs, at a "suitable distance" from the FPGA's pin.

 

I am assumed that the rising edge is around 0.5ns for a 750Mb/s 1280x720p signal. That gives a 1/4th Transition Electrical Length is about 2cm, and using my trusty scrap of paper the trace from the chip to the top of the wing connector is about 5cm.

 

So I am now worried that if I locate the termination that far from the FPGA it will adversely affect the signal integrity. Can anybody confirm if this worry is well founded or not? 

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Hi Tom,

 

Looking at page 29, "The TMDS standard requires external 50Ω resistor pull-ups to 3.3V on inputs.", and reading up on UNTUNED_SPLIT_25/50/75 the resistance is connected to Vcco/2, where as TMDS requires that the 50 ohm needs to be connected to only 3V3.

 

TMDS seems to be odd - rather than LVDS where the driver's power rail provides the current, with TMDS the current always flows from the receiver's power rail to the transmitter. From what I can tell, the transmitter works like an open collector driver, where the the current being sunk is carefully controlled to pull just the right amount for the impedance of the cable and source termination. The 50 ohm at the receiver should make it look to the transmitter like an infinitely long 50 ohm cable connected to 3V3.

 

http://www.design-reuse.com/articles/22347/transmitter-phy-hdmi.html 

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Some jitter and phase difference is allowed. But yes, this is tricky.

 

Eventually I'll test the HDMI receiver, currently it's really not possible for me (no free time at all).

 

Alvie

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Built two boards last night - one was trashed due to a misaligned  HDMI connector, the other is looking OK. Haven't powered it up yet!

 

post-29512-0-79757600-1407355633_thumb.j

 

Only problem so far is that the HDMI connector holes are a little bit too big... and yes, I also need to get some nice clean solder for attaching the pins, not my fifteen year old through-hole stuff!

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I hit a brick wall on this for a couple of days - it locked correctly but no HSYNC or VSYNC was being detected by my TV. I've lent my 'scope to a friend to fix his stereo so decided to play with smart LEDs instead.

 

However I had an minor epiphany tonight while getting the boy ready for bed - was looking for the wrong channel for the HSYNC and VSYNC signals. D'oh!

 

Here's the test setup - Pipistrello generating HDMI (powered over the HDMI cable's 5V line! :-/ ), over to my HDMI input wing, then into the Papilio Pro, and out via the 8 bit analogue VGA  output of the LogicStart.

 

post-29512-0-40611300-1408869274.jpg

 

Holy C@#p - it works!

 

post-29512-0-84327500-1408869413.jpg

 

Still a few little random pixel-level issues here and there. Looks like timing between clock domains and/or phase of the capture bit clock.

 

post-29512-0-36996200-1408869475.jpg

 

But on the other hand, the errors look consistent between each colour channel - somewhere around the middle of the LSB. Might be a TMDS decode issue.

 

I am stoked. 

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So, I did a little more testing. When powered by a USB Powerbank's 1A output, with it turned on I get errors:

 

post-29512-0-70439200-1408875398.jpg

 

When I turn the power bank off, it is pixel perfect.

 

[post-29512-0-35807600-1408875504.jpg

 

Humm... now that is really interesting. So is the power supply causing additional phase noise? Is the change in operating conditions changing delays?  

 

Time to read up on IDELAY2 and see if I can tune out the errors.

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A little bit of tweaking the phase (by 5 degrees of the pixel clock, or 50 degrees of the bit clock and the picture is stable. Now to work out how to work out how to do that reliably in hardware...

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Great! Can I buy your wing somewhere?

 

Well, I've got eight more spare PCBs (a batch of 10 was $20) - I can post you one if you want to assemble it - just PM me your address.

 

If you want me to assemble it I'm more than happy to do one or two, but you'll have to send your address to me on the back of a post card to make it worth my while (or ask really nicely).

 

If enough people ask, maybe Jack will want to make a small batch once I've got everything working?

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HI,

 

just a thought: phase noise can result from an additive noise component: A clock waveform with limited slew rate gets shifted up and down by low-frequency noise, and the crossing point through the switching threshold is modulated.

i'd try some ferrite beads. SMPS supplies are generally noisy.

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Well, I've got eight more spare PCBs (a batch of 10 was $20) - I can post you one if you want to assemble it - just PM me your address.

If you want me to assemble it I'm more than happy to do one or two, but you'll have to send your address to me on the back of a post card to make it worth my while (or ask really nicely).

If enough people ask, maybe Jack will want to make a small batch once I've got everything working?

perhaps we can trade? I think i have some spare papilio pro pcbs if you want one?

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Update on progress.

  • The board works perfectly at 640x480 (250Mb/s per channel).
  • It works perfectly when driven by a Pipistrello @ 1280x720 (720p - 750Mb/s per channel), although is very sensitive to clock phase.
  • It almost works perfectly at at 1280x720, when receiving signals from a Western Digital HD Live - but a selected few bit patterns are not correctly received.

I'm playing around with an IODELAY2 to dynamically tune the per-channel delay, but the blue channel remains very stubbon and refuses to become error-free.

 

Google found me a reference in Altera's documentation (http://www.altera.com/literature/hb/stx2/stx2_sii52012.pdf) that "For a 1-ns rise-time edge, the stub length should be less than 0.5 inches [12mm]". I guestimate that I have about 30mm, and given that the rise time for DVI-D is less than 0.4 bit time (about 0.5ns @ 720p) I don't think I'm going to win this battle.

 

If I was really desperate, it could tombstone the resistors on the underside of the headers of the papilio pro, and use a solid wire jumper to attach the top end to the 3v3 line. That will get them a maybe 12mm closer to the FPGA. However, I'm not that desperate.to attack a board with a soldering iron.

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I attempted to build three wings last night for those who asked. Here they are prior to reflow

 

post-29512-0-32705600-1409799380_thumb.j

 

My HDMI connector reflow skills are lacking. I put the line of solder paste in the wrong place and I ended up with solder bridges trapped under the connector. I might have slavaged two with a little solder wick. Will update as when I get a chance to go over the boards with my meter.

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Two of the three boards were successfully salvaged and have tested fine. One is already off to The Netherlands. 

 

Now to work on the EDID functionality....

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