Gasp

New Papilio One 500K User - Spartcam

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Hi everyone !

 

I'm looking on using the Papilio One 500K board with the camera OV7670. I downloaded the source code from the Voelker's project but I don't manage to pick out the good information to plug the camera on the board. The ucf file seems to mean that the camera is connected on wing C, but the first picture showing the board and OV7670, it seems to be connected on wings BH/AL...

 

First time I try to develop on FPGA from square one, so firsts steps are quite hard for me... I have good basics on VDHL but all stuff like pins, constraints files etc are pretty unknown for me...

 

Any help would be appreciated !

 

Thanks :)

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Hi ! I managed connecting camera on Papilio and display frames through the VGA Wing of Arcade Megawing. This VGA output can display 4096 colours (4 bits for each RGB value).

 

The problem is I don't have a proper image on screen... I would like to display a RGB output and I'm a bit lost on how configuring properly internal registers in the camera. The vga controller I use comes from Mike Field's project here : http://hamsterworks.co.nz/mediawiki/index.php/OV7670_camera

 

Gasp.

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Plus, during implementation of the top module, this mesage appears : 

 

WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
   clock site pair. The clock component <OV7670_PCLK_BUFGP/BUFG> is placed at site <BUFGMUX_X1Y0>. The IO component
   <OV7670_PCLK> is placed at site <P26>.  This will not allow the use of the fast path between the IO and the Clock
   buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <OV7670_PCLK.PAD>
   allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
   The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that
   this error condition be corrected in the design.
 
Is that a critical problem ?

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BTW, I looked at Mike's ucf file and it looks like he had the same problem:

NET "OV7670_PCLK" CLOCK_DEDICATED_ROUTE = FALSE;

In general, a clock input in that frequency range (~24 MHz) should use a dedicated clock input pin.

 

Magnus

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Ok thanks Magnus, it fixed my warning on ISE.

 

But for now, I spent few days trying to set properly the camera registers in order to obtain 640x480 RGB Raw Bayer pixels trough the camera, but without any results... I know that I need to use the SCCB interface and set registers values with corresponding adresses in camera. I follow the instructions given in the "Implementation guide"' page 11 but I don't have a good image on screen !

 

Another question, maybe a little naive, but I would want to understand : I know there is a link between the scale of the frame given by the sensor (in my case, 640x480) and the size of the memory. As I have seen until today, it seems that to display properly a frame on screen, the memory has to save an entire frame. So it represents 640x480 = 307200 pixels ! According to the available memory on the Papilio One 500K (40 Kbytes), it then appears that it's impossible. Am I wrong ?

 

All these things are pretty blur to me, so any help would be really appreciated.

 

Gasp.

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Mike's project only uses 160x120 pixels from the camera which is 19200 pixels.  He stores that as "RGB 3-3-2" so he needs a 19200 byte frame buffer.

He is then pixel-replicating this in the VGA controller.  Here is the comments for the VGA controller in his code:

------------------------------------------------------------------------------------ Engineer: Mike Field <hamster@snap.net.nz>-- -- Description: Generate analog 800x600 VGA, double-doublescanned from 19200 bytes of RAM------------------------------------------------------------------------------------

Hope this helps,

Magnus

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