Grant Searle's Multicomp

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This was on the homepage a while ago:




I came across the system while searching for a soc that would be 

-8bit (preferably z80 so i can actually understand it:)

-has a serial console as the IO device

-simple enough toplevel so it would not require a complete rewrite to extend with other peripherals requiring different clocking.


Finding this was like hitting a jackpot as in addition to supporting the requirements I had you can optionally use VGA/ps2 as the IO device

and the system actually supports three different cpus with very minor changes (z80/6809/6502) 

...and to top it all there is a basic interpreter supplied for every cpu arch.

Which of course can easily be replaced by another monitor rom, or a compiled program could be permantenly inserted in the 'userspace' memory for debugging.



The downside is it is targeted at an Altera device so it requires some very minor changes to compile.

I can attach a toplevel+generic ram definitions for a ppro if someone wants them.


... a late high five to Matthew H - this was the easiest test bench I could find to play with your published SDRAM interface :D






ps. do take a look at the entire website, some of the older projects are really cool.

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Ooohhh, thanks for bringing that up again. It would be great to have a working version for the Papilio Pro, even better, I'd love to integrate it into the schematic library...



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This looks nifty, having gotten back to messing with FPGAs I came here to post it and then found it already here. Has anyone got it up and running on the Papilio boards yet? Other than the BRAM blocks and clock generation the code looks fairly generic.

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