Corey Kosak

Newbie project #3 - animated shapes

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Hi folks,

 

I thought I'd share my third project with you all. I got sort of obsessed with the idea of driving the VGA protocol without any frame buffer memory backing the display (note 1) and I wanted to see how far I could get with such a design. I ended up with a cute little program that bounces a few geometric shapes around the screen and also does boundary and collision detection.

 

There's a YouTube video here (http://youtu.be/ltEPILMaUMk) and the source code is here: https://github.com/kosak/PapilioPro-AnimatedShapes

 

Feedback on the code is very welcome. I'm a newbie VHDL programmer and I find the language sort of frustrating so I sort of made up my own coding conventions and did some other hacks. I also agonized a lot about how modular such a design should be and how inter-module communication should work.

 

In the process I've also generated a bunch of VHDL questions which I hope to post somewhere, if y'all don't mind. The first is hopefully an easy one: I used the IP Core generator to get a 25.175MHz pixel clock and it crapped out a huge number of files into my ipcore_dir. I'm sure most of those do not need to be checked into source control. Can you tell me which ones are supposed to be checked in?

 

Thanks for looking at my demo!

 

(note 1) mostly because I'm intimidated by the SDRAM :-)

 



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You must have a different definition of Newbie to most :-) Well done!

 

About those 'junk' files. You will most probably find a generated VHDL file that contains all the PLL and clock buffers. I usually remove the CoreGen IP from my project, then add back in the VHDL file.

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Corey,

 

Awesome job! I'm going to put this in the showcase and up on the blog this week.

 

Like hamster says, its much nicer to convert anything made with coregen into VHDL files, trying to check in the coregen files always gets ugly and people end up having to regenerate the cores and half the time it doesn't work. It sounds like hamster finds the vhdl files that are generated in the coregen folder, that might be easier then the method I use. Normally I click on the coregen item and then under the processes window I click on the View HDL Functional Model process which shows the VHDL file. I save that in my project and then click on the View HDL Instantiaion Template which gives you the code you need to place in your top level VHDL file in order to instantiate it into you project. Then I delete the coregen file from the project.

 

Also, I normally use a gitignore for Xilinx projects.

https://gist.github.com/mapedd/2045092

 

Jack.

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Wow, that worked great. I'm so glad to be rid of that ipcore_dir. And that .gitignore is priceless!

 

What about the iseconfig directory? I don't see that in the .gitignore, but I'm thinking that directory is also unnecessary. What do you think?

 

Also I seem to have inherited a new VGAClock.sym file (https://github.com/kosak/PapilioPro-AnimatedShapes/blob/master/source/VGAClock.sym ). Not sure what I did to get that. Maybe I fat-fingered something.

 

Anyway, thanks!!

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By the way, as I was building this project I started collecting a list of frustrations where I found myself blocked by the language.

 

I was quite surprised to see that there are certain constructs allowed in modern VHDL that are not supported by our Xilinx compiler. In some cases these are just nice-to-haves, but in other cases the lack of these features really blocked me from writing my code the way I needed to.

 

I'm happy to explain what I mean in detail, but as a top-level question I was wondering: are there more sophisticated toolchains available, and if so, would the existence of such toolchains influence your decision on which chip to use for the next Papilio?

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Here is one example that gets my goat. I can, with some verbosity, make a two-dimensional signal "sig" which is parameterized by n and w, but there's no way do the same for the input port "data" using the version of VHDL that we have.

 

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Main is  generic (n: positive := 3; w: positive := 8);  port (    --Uncomment the below to see the error.    --data: in array(0 to n-1) of std_logic_vector(w-1 downto 0);    clk: in std_logic  );end Main;architecture Behavioral of Main is  subtype myvec_t is std_logic_vector(w-1 downto 0);  type sig_t is array(0 to n-1) of myvec_t;  signal sig: sig_t;beginend Behavioral;

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Hello,  A very neat project!

 

Hmm, In your example above, in my experimentation, it is the array use and not the generic use that appears to cause problems.  I do agree generics aren't quite as useful as they could be in VHDL (and I miss having a preprocessor for some macros and conditional stuff too).

 

Also, you probably are already aware but ISE has a setting to use VHDL-200X but it defaults to VHDL-93 version of the language I believe.

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You can safely include the iseconfig directory in your gitignore file. The sym file is a symbol for use in the schematic editor, so you can get rid of that too.

 

One thing to keep in mind with VHDL is that it was originally developed to simulate hardware and was later adapted to synthesizing hardware. When you synthesize hardware it is always a subset of the VHDL language because the hardware itself imposes limitations. So you have to be careful when looking at VHDL or Verilog examples to determine if they are meant for simulation or synthesis.

 

Jack

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No, I'm afraid I must disagree. The evidence I have shows that two-dimensional arrays work just fine (I even have a cite (somewhere) in the Xilinx manual saying they work fine). The problem is with generics.

 

Specifically, in the below code, the two-dimensional array "data1" synthesizes perfectly well. But the problem is when I try to specify the type all on one line (see data2) and when I try to specify the dimensions generically (see data3).

 

The former is a minor inconvenience; the latter is a pretty awkward blocker.

 

I'm (pretty) sure that modern VHDL supports the data3 syntax (and can synthesize it) or something similar. The problem is this particular Xilinx toolchain we're using. Hence my question about alternative toolchains.

 

This is the code. data1, a two-dimensional array, synthesizes just fine. data2 and data3 do not compile.

 

library IEEE;use IEEE.STD_LOGIC_1164.ALL;package whatever is  subtype myvec_t is std_logic_vector(7 downto 0);  type sig_t is array(0 to 2) of myvec_t;end whatever;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use work.whatever.all;entity Main is  generic (n: positive := 3; w: positive := 8);  port (    data1: sig_t;  -- a 2D array. synthesizes just fine.    --data2: array(0 to 2) of std_logic_vector(7 downto 0);  -- does not compile    --data3: array(0 to n-1) of std_logic_vector(w-1 downto 0);  -- does not compile, alas    clk: in std_logic  );end Main;architecture Behavioral of Main isbeginend Behavioral;

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Well, according to this article you can do the following, will that do what you are looking for?

library IEEE;use IEEE.STD_LOGIC_1164.ALL;package whatever is  type Matrix_n_by_8 is array (natural range<>) of STD_LOGIC_VECTOR (7 downto 0);  type Matrix is array(natural range<>, natural range<>) of std_logic;end whatever;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use work.whatever.all;entity Test is  generic (n: positive := 3; w: positive := 8);  port (	 data1: in Matrix_n_by_8(n-1 downto 0);	 data2: in Matrix(n-1 downto 0, w-1 downto 0);    clk: in std_logic  );end Test;architecture Behavioral of Test isbeginend Behavioral;

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>> . I'm a newbie VHDL programmer and I find the language sort of frustrating

 

"sort of" frustrating would be for me a mild understatement... have a look at Verilog :-)

It's a coke-vs-Pepsi battle. Generally, Verilog will do the same job with fewer keystrokes. It is often surprising how little substance remains if one strips away all the bloat.

Best enjoyed close to the hardware it's supposed to describe. (IMHO).

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